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[VHDL-FPGA-Verilog] random data gen（vhdl） DL : 0: 任意数据发生器的源代码-arbitrary data source code generator
Date : 2025-12-31 Size : 95kb User : 王锋
[VHDL-FPGA-Verilog] VHDL_UART DL : 0: VHDL语言的UART串行接口芯片程序,包括数据接收器、数据发送器和波特率发生器等。-VHDL language UART serial interface chip procedure, including data receiver, data transmitter and baud rate generator and so on.
Date : 2025-12-31 Size : 3kb User : liukun
[VHDL-FPGA-Verilog] VHDL-ROM4 DL : 0: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Date : 2025-12-31 Size : 96kb User : 宫逢源
[VHDL-FPGA-Verilog] DDS DL : 0: 基于EPM7128的数字合成信号发生器（DDS）设计。通过对EPM7128编程，组合出地址累加器、数据锁存器、256*8位ROM空间。外接DA可实现正弦波输出功能-EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space. DA external sine wave output function can be realized
Date : 2025-12-31 Size : 346kb User : xiaoyu
[VHDL-FPGA-Verilog] Multi_function_waveform_generator DL : 0: 多功能波形发生器VHDL程序与仿真.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。 -Multi-function waveform generator and simulation of VHDL procedures. The realization of four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and magnitude of control output (square wave of duty cycle A is controllable), Arbitrary Waveform characteristics can store data and can reproduce the waveform, but also the completion of the linear superposition of a variety of output waveforms.
Date : 2025-12-31 Size : 10kb User :
[VHDL-FPGA-Verilog] waveform-generator-o-VHDL-program DL : 0: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 -Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is controlled), can store arbitrary waveform feature data and can to reproduce the waveform, it can perform- all kinds of linear superposition of the output waveform.
Date : 2025-12-31 Size : 10kb User : 刘新
[VHDL-FPGA-Verilog] hdb DL : 0: 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。基于达到达到达到的信号发生器的源程序-Digital baseband signal transmission is a digital communications system, an important component. In digital communication, there are some occasions, may from time through the carrier modulation and demodulation process, the base-band signal for direct transmission. AMI code signal using alternating inversion, there may be four to zero with the phenomenon, which is not conducive to the receiving end of the timing signal extraction. The HDB3 code because of its non-DC components, low-frequency components, and even a small number of 0 up to more than three characteristics, while the timing signal recovery is very favorable, and has become CCITT Association recommended one of baseband transmission pattern. In this paper the use of VHDL language for data transmission system in the HDB3 encoder has been designed. Based on the signal generator to achieve to reach to reach the source
Date : 2025-12-31 Size : 3kb User : 成风
[VHDL-FPGA-Verilog] usefulUART DL : 0: UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA器件设计与实现UART。 -UART is a widely used serial data communication circuits. This design includes UART transmitter, receiver and baud rate generator. Design and Application of EDA technology, based on FPGA device design and implementation of UART.
Date : 2025-12-31 Size : 4kb User :
[VHDL-FPGA-Verilog] VHDL(sin) DL : 0: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Date : 2025-12-31 Size : 17kb User : 爱好
[VHDL-FPGA-Verilog] UARTVHDL DL : 0: UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA/CPLD器件设计与实现UART。-UART is a widely used serial data communication circuit. The design includes UART transmitter, receiver and baud rate generator. Application of EDA design technology based on FPGA/CPLD device design and implementation of UART.
Date : 2025-12-31 Size : 236kb User : 王志慧
[VHDL-FPGA-Verilog] crc-gen DL : 0: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
Date : 2025-12-31 Size : 59kb User : badfox
[VHDL-FPGA-Verilog] interweave_1 DL : 0: 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data.
Date : 2025-12-31 Size : 36kb User : 李修函
[VHDL-FPGA-Verilog] VHDL DL : 0: 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register with the state controller clk, the clock signal clk2 sent to the data controller and the state controller, the signal sent to fetch the data controller and address of the multiplexer, the signal sent to the arithmetic logic unit alu_clk.
Date : 2025-12-31 Size : 4kb User : cccs
[VHDL-FPGA-Verilog] FPGA-VHDL-DDS DL : 0: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Date : 2025-12-31 Size : 1.2mb User : 许聪
[VHDL-FPGA-Verilog] fpdpsk DL : 0: FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode converter) 6
Date : 2025-12-31 Size : 2kb User : hucy
[VHDL-FPGA-Verilog] RISC_CPU DL : 0: VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator, arithmetic and logic unit, the data controller, the state controller, the program counter and address multiplexer
Date : 2025-12-31 Size : 6kb User : 林琳
[VHDL-FPGA-Verilog] fsk_tz DL : 0: vhdl实现FSK调制，本次毕业设计的数据速率 1.2kb/s，要求产生一个1.2kHz的正弦信号，对正弦信号每周期取100个采样点，因此要求产生3个时钟信号：1.2kHz（数据速率）、120kHz（产生1.2kHz正弦信号的输入时钟）、240kHz（产生2.4kHz正弦信号的输入时钟）。基准时钟已由一个外部时钟120MHz提供，要得到前面三种时钟，就需要首先设计一个模50的分频器产生240kHz信号，再设计一个二分频器，生产一个120kHz的信号，然后再前面的基础上再设计一个模100的分频器，用来产生1.2kHz的随机信号产生速率。-vhdl achieve FSK modulation, the graduate design data rate of 1.2kb/s to produce a sinusoidal signal of 1.2kHz, take the 100 sampling points per cycle of the sinusoidal signal, thus requiring to produce the three clock signals: 1.2 kHz (data rate , 120kHz, a 1.2kHz sine input clock signal), 240kHz (a 2.4kHz sine signal input clock). 120MHz reference clock has been an external clock to get the first three clock, you need to first design a mold 50 of the divider to produce a 240kHz signal, re-design of a two frequency divider to produce a 120kHz signal, and then the front of the base on the re-design of a mold 100 of the divider used to generate the 1.2kHz random signal generator rate.
Date : 2025-12-31 Size : 1kb User : 杨
[VHDL-FPGA-Verilog] VHDL-book3 DL : 0: D_flipflop：1位D触发器的设计 D_fllipflop_behav：4位D触发器的设计 reg1bit：1位寄存器设计 reg4bit：4位寄存器设计 shiftreg4：一般移位寄存器的设计 ring_shiftreg4：环型移位寄存器的设计 debounce4：消抖电路的设计 clock_pulse：时钟脉冲电路的设计 count3bit_gate：3位计数器的设计 count3bit_behav：3位计数器的设计 mod5cnt：模5计数器的设计 mod10Kcnt：时钟分频器的设计 morsea：任意波生成器的设计 sw2reg：加载开关量到寄存器的设计 shift_reg8：移位数据到移位寄存器的设计 scroll：滚动7段数码显示设计 fib：Fibonacci序列设计 pwm4：PWM控制直流电机设计 pwmg：PWM控制伺服电机位置设计-D_flipflop: 1-bit D flip-flop design D_fllipflop_behav: 4-bit D flip-flop design reg1bit: 1-bit register design reg4bit: 4-bit register design shiftreg4: general shift register design ring_shiftreg4: ring shift register design debounce4: elimination shake circuit design clock_pulse: clock pulse circuit design count3bit_gate: 3-bit counter design count3bit_behav: 3-bit counter design mod5cnt: Mode 5 counter design mod10Kcnt: clock divider design morsea: arbitrary waveform generator design sw2reg: Load switch to register the design shift_reg8: shift data into the shift register design scroll: Scroll 7-segment digital display design fib: Fibonacci Sequence Design pwm4: PWM controlled DC motor design pwmg: PWM servo motor position control design
Date : 2025-12-31 Size : 8.6mb User : 贾诩
[VHDL-FPGA-Verilog] myproj DL : 0: 使用vhdl语言设计波形发生器，产生正弦波，方波，三角波，锯齿波，实现频率，幅度可调。项目包附有设计说明和资料。-Waveform generator using vhdl language design, produce sine, square, triangle, ramp, realize the frequency, amplitude adjustable. Project package with design specifications and data.
Date : 2025-12-31 Size : 15.39mb User : 李伟杰
[VHDL-FPGA-Verilog] VHDL DL : 0: 正弦波发生器代码VHDL 其中包括分频正弦波数据-Sine wave generator VHDL code Divide the sine wave data including
Date : 2025-12-31 Size : 7kb User : 123456789

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