Introduction - If you have any usage issues, please Google them yourself
vhdl achieve FSK modulation, the graduate design data rate of 1.2kb/s to produce a sinusoidal signal of 1.2kHz, take the 100 sampling points per cycle of the sinusoidal signal, thus requiring to produce the three clock signals: 1.2 kHz (data rate , 120kHz, a 1.2kHz sine input clock signal), 240kHz (a 2.4kHz sine signal input clock). 120MHz reference clock has been an external clock to get the first three clock, you need to first design a mold 50 of the divider to produce a 240kHz signal, re-design of a two frequency divider to produce a 120kHz signal, and then the front of the base on the re-design of a mold 100 of the divider used to generate the 1.2kHz random signal generator rate.