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[VHDL-FPGA-Verilog] 20051113104111170 DL : 0: FPGA的VHDL设计经验总结《小型微型计算机系统》2003年7月-FPGA VHDL design experience, "small micro-computer system," July 2003
Date : 2025-12-30 Size : 194kb User : 天天
[VHDL-FPGA-Verilog] magnitude DL : 0: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Date : 2025-12-30 Size : 12kb User : 郝晋
[VHDL-FPGA-Verilog] computer5 DL : 0: 一种RISC结构8位微控制器的设计与实现-The structure of a RISC micro-controller' s 8 Design and Implementation
Date : 2025-12-30 Size : 8.04mb User : steven
[VHDL-FPGA-Verilog] cpu DL : 0: 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
Date : 2025-12-30 Size : 1.21mb User : Rachel
[VHDL-FPGA-Verilog] logic_app DL : 0: 中际赛微15期培训班逻辑功能试验 2009-5-Competition in 15 micro-logic function tests training 2009-5
Date : 2025-12-30 Size : 1.16mb User : xinzhi
[VHDL-FPGA-Verilog] vhdl DL : 0: A vhdl implementation of 8051 micro controller. this code is from oregano.
Date : 2025-12-30 Size : 98kb User : baba
[VHDL-FPGA-Verilog] micro DL : 0: 16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Date : 2025-12-30 Size : 30kb User : mojo
[VHDL-FPGA-Verilog] pico_code DL : 0: pico blaze VHDL code for write to micro SD flash with spi protocol
Date : 2025-12-30 Size : 19kb User : ali
[VHDL-FPGA-Verilog] Microprogramcontroller DL : 0: 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
Date : 2025-12-30 Size : 735kb User : 糖糖
[VHDL-FPGA-Verilog] can_latest[1].tar DL : 0: CAN，全称“Controller Area Network”，即控制器局域网，是国际上应用最广泛的现场总线之一。最初，CAN被设计作为汽车环境中的微控制器通讯，在车载各电子控制装置ECU之间交换信息，形成汽车电子控制网络。比如：发动机管理系统、变速箱控制器、仪表装备、电子主干系统中，均嵌入CAN控制装置。 -CAN, full name of the " Controller Area Network" , the Controller Area Network, is internationally the most widely used field bus. Initially, CAN is designed as a vehicle environment, the micro-controller communications, in-vehicle electronic control unit ECU of the exchange of information between the formation of automotive electronic control network. For example: engine management systems, transmission controllers, instrumentation and equipment, electronic backbone of the system are embedded CAN control.
Date : 2025-12-30 Size : 1.1mb User : zhaohaiting
[VHDL-FPGA-Verilog] Micro_uart DL : 1: Micro-uart source code
Date : 2025-12-30 Size : 1.4mb User : Huang
[VHDL-FPGA-Verilog] controlvhdl DL : 0: 一个四位微程序控制器的指令译码器源码，运用VHDL语言实现。-A four micro-program controller instruction decoder source code, the use of VHDL language.
Date : 2025-12-30 Size : 8kb User :
[VHDL-FPGA-Verilog] CPU-exp DL : 0: 基于VHDL编写的CPU程序，用微程序的方式实现。内含说明本程序的说明文档。-CPU program written in VHDL, with the micro-program ways.Containing the document of the program.
Date : 2025-12-30 Size : 1.24mb User : gy
[VHDL-FPGA-Verilog] std_1076 DL : 0: VHDL标准介绍，热衷于语法及标准写法的定义，微电子具有很高的参考价值-VHDL standard introduction, keen on grammar and writing standards for the definition of micro-electronics with high reference value
Date : 2025-12-30 Size : 10.56mb User : 李仕意
[VHDL-FPGA-Verilog] The--VHDL-code-of-I2C DL : 0: 该程序采用延时接收比较来实现仲裁的方法，使不具有I2C接口的普通微控制器（MCU）能够实现模拟I2C总线的多主通信。-This program is to realize the delay receiving the arbitration method, do not have the I2C interface of ordinary micro controller (MCU) can simulate the I2C bus more than the main communication.
Date : 2025-12-30 Size : 4kb User : 西土瓦
[VHDL-FPGA-Verilog] micro-processor DL : 0: 这是一个8位微处理器的vhdl设计代码。-This is the design of a 8-bit micro-processor.
Date : 2025-12-30 Size : 4kb User : baoshu
[VHDL-FPGA-Verilog] Micro DL : 0: build micro with verilog/vhdl
Date : 2025-12-30 Size : 883kb User : Hamid
[VHDL-FPGA-Verilog] myfpga DL : 0: 详细描述设计过程 ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述（评分重点） ⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义） ⑦ 实验总结，在调试和下载过程中遇到的问题 -Design Process Design ② ① instruction format defined micro-operation ③ ④ processor division beat a detailed description of the structural design and function block diagram (score focus) a detailed description single wire connection between modules with thin lines, 2 and above with crude line and mark the number and. b. Use the arrow indicating the flow of data, signal names used in cases of functional modules shall be marked ⑤ structural design diagram and functional description (score focus) ⑥ VHDL code on connection, UCF file test instruction sequence (the meaning of each instruction) ⑦ experiments summarized in debugging and downloading problems encountered in the process
Date : 2025-12-30 Size : 5.97mb User : 王思雨
[VHDL-FPGA-Verilog] lab6 DL : 0: 详细描述设计过程和实验中遇到的问题，包括： ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述（评分重点） ⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义）实验总结，在调试和下载过程中遇到的问题 -A detailed description of the design process and problems encountered in the experiment, including:. ① ② micro-operation instruction format design definition ③ ④ processor division beat detailed description of the structural design and function block diagram (score focus) a single-wire connection between modules with a thin, two more than the number indicated by bold lines and and. b. Use the arrow indicating the flow of data, signal names used when instantiated ⑤ shall be marked on the connection of each functional module design and function block diagram and description (Ratings Key) ⑥ VHDL code, UCF file, test instruction sequence (the meaning of each instruction) experiments summarized problems encountered during commissioning and download the
Date : 2025-12-30 Size : 5.58mb User : 王思雨
[VHDL-FPGA-Verilog] ccsuemupc条件跳转(1) DL : 0: 设计一个模型机，具体设计要求如下：（1）设计指令系统，要求有取数指令、加法指令、跳转指令、停机指令等（2）设计指令格式、微指令格式、微程序、时序电路、数据通路，完成cpu的设计。（3）利用模块化设计，分别设计存储器模块、运算器模块、时序电路模块、微程序控制器模块、显示模块等，最后进行系统的顶层设计，完成复杂模型机的设计与实现测试（4）根据任务，完成主程序的设计，同时把主程序翻译成目标代码，写入主存，仿真下载测试。(Design a model machine, the specific design requirements are as follows: (1) design instruction system, required to have number instructions, addition instructions, jump instructions, downtime instructions and so on (2) Design instruction format, micro-instruction format, micro-program, time series circuit, data path, complete the design of the CPU. (3) The use of modular design, respectively design memory module, operator module, time series circuit module, microcontroller Controller module, display module, etc., and finally carry out the top layer design of the system, complete the design and implementation of complex model machine test (4) According to the task, complete the design of the main program, while translating the main program into the target code, Write the deposit, simulation download test.)
Date : 2025-12-30 Size : 1.13mb User : 12332122