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[VHDL-FPGA-Verilog] mimasuo DL : 0: 设计一个具有较高安全性和较低成本的通用电子密码锁，其具体功能要求如下：(1) 数码输入：每按下一个数字键，就输入一个数值，并在显示器上的最右方显示出该数值，同时将先前输入的数据依序左移一个数字位置。(2) 数码清除：按下此键可清除前面所有的输入值，清除成为“0000”。(3) 密码更改：按下此键时会将目前的数字设定成新的密码。(4) 激活电锁：按下此键可将密码锁上锁。(5) 解除电锁：按下此键会检查输入的密码是否正确，密码正确即开锁。 -Design of a high security and lower-cost generic electronic locks, its specific functional requirements are as follows: (1) Digital Input: Each press a number key, you enter a numeric value, and the display on the far right shows out the value, while the previous input data in sequence left a number of locations. (2) Digital Clear: Press this key to clear all the previous input values, clear as " 0000." (3) password change: press this key will set the current figure into a new password. (4) to activate electric locking: Press this key lock can be unlocked. (5) The lifting of electric locking: Press this button will check the password is correct, the password is correct that the unlock.
Date : 2025-12-25 Size : 2kb User : kxsh
[VHDL-FPGA-Verilog] czcjfxt DL : 0: 实现计费和显示的功能：（1）费用的计算（2）里程，即汽车行驶里程（3）等候时间（4）费用-To achieve billing and display functions: (1) the cost of computing (2), mileage, or vehicle mileage (3) waiting time (4) Fees
Date : 2025-12-25 Size : 517kb User :
[VHDL-FPGA-Verilog] cordic DL : 0: we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time application of fingerprint recognition. We present our VHDL description of CORDIC algorithm. To reduce iteration delay, we used some combinatory blocks. Fixed point arithmetic was considered. To valid our conception and its CORDIC accuracy, we present relative error calculated in convergence range for some trigonometric and hyperbolic functions. Our architecture was implemented and tested. The contribution of the paper includes the CORDIC design flow. -we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time application of fingerprint recognition. We present our VHDL description of CORDIC algorithm. To reduce iteration delay, we used some combinatory blocks. Fixed point arithmetic was considered. To valid our conception and its CORDIC accuracy, we present relative error calculated in convergence range for some trigonometric and hyperbolic functions. Our architecture was implemented and tested. The contribution of the paper includes the CORDIC design flow.
Date : 2025-12-25 Size : 2kb User : Nihel Neji
[VHDL-FPGA-Verilog] 2 DL : 0: EDA的课程设计，利用VHDL语言、PLD设计基于FPGA的出租车计费系统，选用ALTERA公司低功耗、低成本、高性能的FPGA芯片EPF10K10，以MAX+PLUSⅡ软件作为开发平台，设计了出租车计费器系统程序并进行了编译，功能仿真和下载。使其实现计费以及预置和模拟汽车启动、加速、停止、暂停等功能，并动态扫描显示车费数目。-EDA curriculum design, the use of VHDL language, PLD design FPGA-based taxi billing system, the company selected ALTERA low power, low-cost, high-performance FPGA chip EPF10K10, the MAX+ PLUS Ⅱ software as a development platform, design a taxi billing system and make the compilation process, functional simulation, and download. To achieve automotive billing and pre-and simulation start, accelerate, stop, pause and other functions, and the number of dynamic scans indicate the fare.
Date : 2025-12-25 Size : 8kb User : wang
[VHDL-FPGA-Verilog] ES8388-DS DL : 0: 低功耗立体声音频编解码器带耳机放大器 ES8388是一种高性能，低功耗和低成本的音频编解码器。它由2通道ADC，2通道DAC，麦克风放大器，耳机放大器，数字声音效果，并模拟混合和增益功能。-Low Power Stereo Audio CODEC With Headphone Amplifier ES8388 is a high performance, low power and low cost audio CODEC. It consists of 2-ch ADC, 2-ch DAC, microphone amplifier, headphone amplifier, digital sound effects, and analog mixing and gain functions.
Date : 2025-12-25 Size : 726kb User : 曾小军
[VHDL-FPGA-Verilog] time4clock2 DL : 0: 秒表/时钟计时器是在一种计时器上实现两种基本功能的一种器件。它广泛应用于各种场所，同时，它以其小巧，价格低廉，走时精度高，使用方便，功能多，便于集成化。-Stopwatch/clock timer is a device on a timer to achieve two basic functions. It is widely used in various places, the same time, its compact, low cost, travel time and high precision, easy to use, multi-functional, easy to integrated.
Date : 2025-12-25 Size : 578kb User : geng
[VHDL-FPGA-Verilog] TAXI_TOLL_1_1 DL : 0: 实现出租车自动计费器能进行LCD1602液晶显示。硬件平台：Xilinx Spartan3E -Use VHDL languange to achieve the automatic taxi meter and display cost,waiting time and distance on the LCD1602 . Hardware platforms: Xilinx Spartan3E
Date : 2025-12-25 Size : 3.01mb User : linjunlan
[VHDL-FPGA-Verilog] CoreFIR_RTL-3.0 DL : 0: actelIP核的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision-actelIPcore fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision
Date : 2025-12-25 Size : 1mb User : 睿宸
[VHDL-FPGA-Verilog] ZStack-CC2530-2.5.1a DL : 0: ZigBee协议适应无线传感器的低花费、低能量、高容错性等的要求。Zigbee的基础是IEEE 802.15.4。但IEEE仅处理低级MAC层和物理层协议，因此Zigbee联盟扩展了IEEE，对其网络层协议和API进行了标准化。Zigbee是一种新兴的短距离、低速率的无线网络技术。主要用于近距离无线连接。它有自己的协议标准，在数千个微小的传感器之间相互协调实现通信。(The ZigBee protocol adapts to the requirements of wireless sensor such as low cost, low energy and high fault tolerance. The basis of Zigbee is IEEE 802.15.4. However, IEEE only deals with low-level MAC and physical layer protocols, so the Zigbee alliance extends IEEE and standardized its network layer protocol and API. Zigbee is a new short distance and low rate wireless network technology. It is mainly used for close range wireless connection. It has its own protocol standard, and realizes communication between thousands of tiny sensors.)
Date : 2025-12-25 Size : 15.05mb User : 叶晨叶晨