actelIPcore fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision

release_3.0\actfirgen.exe
...........\config.txt
...........\CoreFIR.exe
...........\docs
...........\....\CoreFIR_DS.pdf
...........\....\CoreFIR_QS.pdf
...........\fir_const.srm
...........\fir_const_pack.srm
...........\fir_const_tap.srm
...........\fir_const_tb.srm
...........\sample_cfg.txt
...........\README.txt
...........\Config.exe

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