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[VHDL-FPGA-Verilog] 数字电子钟 DL : 0: 数字电子钟此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能； 5. 跑表功能。-digital electronic clock this digital electronic clock with functions include : 1. Time, hours, minutes and seconds display; 2. 12 hours with 24 hours of conversion; 3. On the afternoon show; 4. Right hours, minutes, and seconds school function; 5. Stopwatch functions .
Date : 2025-12-22 Size : 7kb User : 吴健宇
[VHDL-FPGA-Verilog] traffic_1112 DL : 0: 一个交通灯的vhdl语言实现用ＶＣ的　　１．在指定的文件夹内查找某个文件　　　　　２．获取系统文件夹的路径，要求显示windows system temp 当前目录的路径Ｃ语言　　跳马问题：在５＊５的棋盘上，以编号为１的点出发，按日只跳马，要求不重复地跳所有位置，求出符合规则所有跳马的方案　　　　１　　６　　１５　　１０　　２１　　　　１４　９　　２０　　５　　　１６　　　　１９　２　　７　　　２２　　１１　　　　８　　１３　２４　　１７　　４　　　　２５　１８　３　　　１２　　２３ -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23
Date : 2025-12-22 Size : 1kb User : 小三
[VHDL-FPGA-Verilog] CNT_24 DL : 0: 用vhdl实现24小时计数器，方法简单实用。仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
Date : 2025-12-22 Size : 47kb User : dm
[VHDL-FPGA-Verilog] 24miao DL : 0: 24秒倒计时系统（有跑马灯）利用CPLD-24 seconds remaining systems (5,250) using CPLD
Date : 2025-12-22 Size : 284kb User : moding
[VHDL-FPGA-Verilog] 2460100Time DL : 0: 24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~
Date : 2025-12-22 Size : 2kb User : 张春
[VHDL-FPGA-Verilog] spant DL : 0: 一个在spantan3上实现的24路分频VHDL程序，实现方法简单，并且在硬件电路上跑过，可以直接使用。可以进一步修改成PWM程序。-a spantan3 achieved in the 24-way frequency VHDL procedures, simple, and the hardware circuits once ran can be used directly. Can be further modified as PWM procedures.
Date : 2025-12-22 Size : 1kb User : 林海
[VHDL-FPGA-Verilog] MyClockTest DL : 0: 这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function.
Date : 2025-12-22 Size : 495kb User : blacksun
[VHDL-FPGA-Verilog] clock DL : 0: 可以实现时间调节，十二，二十四小时转换，定时，闹钟的时钟-Can be time-conditioning, 12, 24 hours conversion, time, alarm clock
Date : 2025-12-22 Size : 407kb User : 王明
[VHDL-FPGA-Verilog] jpeg.tar DL : 0: This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions.
Date : 2025-12-22 Size : 3.26mb User : Bill Guan
[VHDL-FPGA-Verilog] Time DL : 1: 24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
Date : 2025-12-22 Size : 374kb User : 张苏昕
[VHDL-FPGA-Verilog] FPGA DL : 0: 24秒倒计时设计用于专业篮球比赛有说明和一系列程序代码-24 seconds countdown designed for professional basketball game and a series of procedures has made it clear that the code
Date : 2025-12-22 Size : 9kb User : 米虫
[VHDL-FPGA-Verilog] VHDL DL : 1: （1）用VHDL语言编写程序，在EDA实验板上实现（2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。（3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。用VHDL语言编写程序，在EDA实验板上实现（4）整点报时。（5）. 闹钟功能。（6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function.
Date : 2025-12-22 Size : 4kb User : malon
[VHDL-FPGA-Verilog] ElectronicClockandsimulationwithVHDL DL : 0: 电子时钟VHDL程序与仿真。包括:10进制计数器设计与仿真,6进制计数器设计与仿真,24进制计数器设计与仿真.-Electronic Clock and simulation of VHDL program. Includes: 10 binary counter design and simulation, 6 binary counter design and simulation, 24 binary counter design and simulation.
Date : 2025-12-22 Size : 62kb User : Zhu
[VHDL-FPGA-Verilog] zhangjun DL : 0: 用硬件描述语言实现数字钟的设计，实现正常计时，报整点时数，电台整点报时，12小时制与24小时制转换等功能。其中有代码和仿真结果-Using hardware description languages digital clock design, implement the normal timing, the whole point, the number of newspaper, radio and the whole point timekeeping, 12-hour and 24-hour conversion functions. Including code and simulation results
Date : 2025-12-22 Size : 203kb User : 张军
[VHDL-FPGA-Verilog] Desktop DL : 0: crc校验码verilog代码，24bits，按原理写的代码-cyclic redundancy check 24 bits verilog
Date : 2025-12-22 Size : 1kb User : 陈阳
[VHDL-FPGA-Verilog] 24 DL : 0: 2-4解码器的vhdl描述，行为域的描述，-24 decode
Date : 2025-12-22 Size : 10kb User : limi
[VHDL-FPGA-Verilog] 24 DL : 0: 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
Date : 2025-12-22 Size : 1kb User : 单俍
[VHDL-FPGA-Verilog] C4_24 DL : 0: 24计数器，并用两个7段数码管分别显示个位和十位(24 counter, and digital display)
Date : 2025-12-22 Size : 1.58mb User : 尘之皓
[VHDL-FPGA-Verilog] 2 DL : 0: 设计一个具有时、分、秒计时的电子钟，按24小时计时。要求：（1）数字钟的时间用六位数码管分别显示时、分、秒；（2）用两个控制键，对数字钟分别进行分、时校正；（3）具有仿广播电台整点报时的功能。即每逢59分51秒、53秒、55秒及57秒时，发出4声500Hz低音，在59分59秒时发出一声1kHz高音，它们的持续时间均为1秒。最后一声高音结束的时刻恰好为正点时刻。（4）具有定时闹钟功能，且最长闹铃时间为1分钟。要求可以任意设置闹钟的时、分；闹铃信号为500Hz和1kHz的方波信号，两种频率的信号交替输出，且均持续1秒。设置一个停止闹铃控制键，可以停止输出闹铃信号。（5）输入时钟脉冲的频率为50MHz。(Design an electronic clock with time, minutes and seconds, and time by 24 hours. Requirements: (1) the time of digital clock is shown with six digital tubes, respectively, minutes and seconds; (2) two control keys are used to divide and adjust the digital clock respectively. (3) it has the function of imitating radio station. That means that at 59 minutes, 51 seconds, 53 seconds, 55 seconds and 57 seconds, a 4 500Hz bass is emitted. A 1kHz note is emitted at 59 minutes 59 seconds, and their duration is 1 second. The end of the last treble is exactly the moment of truth. (4) it has a timer function and the longest alarm time is 1 minute. Ask to set the alarm clock at any time. The alarm signal is a square wave signal of 500Hz and 1kHz. The signals of both frequencies alternate and output for one second. Set a stop alarm button to stop the output alarm signal. (5) the frequency of input clock pulse is 50MHz.)
Date : 2025-12-22 Size : 51kb User : LIMBO2K
[VHDL-FPGA-Verilog] 模24计数器 DL : 0: 模24计数器的Quartus II文本输入设计及其test bench(Quartus II text input design and test bench of modulo 24 counter)
Date : 2025-12-22 Size : 2kb User : 13570

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