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[VHDL-FPGA-Verilog] AES_RTL DL : 0: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Date : 2025-12-15 Size : 15kb User : 林夢魔
[VHDL-FPGA-Verilog] simple_3DES DL : 0: 精简3DES加解密算法实现，该3DES加解/密系统以精简硬件结构为目标，与传统的以吞吐率为目标的流水线模式3DES加/解密系统相比，具有消耗硬件资源小，性价比突出的优点。-reduced 3DES algorithm system based on FPGA
Date : 2025-12-15 Size : 2.67mb User : dinxj
[VHDL-FPGA-Verilog] des DL : 0: VHDL实现的DES密码算法的完整的加解密。-DES
Date : 2025-12-15 Size : 7kb User : duzhibo
[VHDL-FPGA-Verilog] rc4 DL : 0: RC4算法，WEP算法，加解密，密钥长度256-RC4 algorithm, WEP algorithm, encryption and decryption
Date : 2025-12-15 Size : 3kb User : shixu
[VHDL-FPGA-Verilog] aes DL : 0: verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
Date : 2025-12-15 Size : 7kb User : xie
[VHDL-FPGA-Verilog] Description-of-DES-with-VHDL DL : 0: 用VHDL描述DES算法用硬件的方式DES加解密体现了硬件编程人一般思想-DES algorithm using VHDL description of the way with hardware DES encryption and decryption hardware programming reflects the general thinking of people
Date : 2025-12-15 Size : 14kb User : lichen
[VHDL-FPGA-Verilog] tmdnishi78 DL : 0: 传统的采用软件方式实现的DES算法会在很大程度上占用系统资源，造成系统性能的下降。DES算法本身并没有复杂的数学计算，在加/解密过程中仅有逻辑运算和查表运算，因而从系统性能和加/解密速度的角度来看，采用硬件实现是个理想的方案。-rilog prepared by the entry of the code for beginners is very easy to understand and contribute to the digital circuit learning FPGA entry improve help
Date : 2025-12-15 Size : 283kb User : yijishan
[VHDL-FPGA-Verilog] AES DL : 0: 利用verilog HDL实现的AES算法，在密码芯片加解密中显示出了突出的优越性-The reference-AES.V which has been uploaded is particularly useful for researchers who are dedicated to the password-chip researching.
Date : 2025-12-15 Size : 8.58mb User : 林涛
[VHDL-FPGA-Verilog] avs_aes_latest[1].tar DL : 0: 数字加解密模块的设计-Digital encryption and decryption module design
Date : 2025-12-15 Size : 408kb User : wt
[VHDL-FPGA-Verilog] aes DL : 0: 此程序完成aes的硬件语言实现部分，通过vhdl语言完成加解密过程。-This process is complete aes hardware language section, vhdl language to complete the encryption and decryption process.
Date : 2025-12-15 Size : 11.6mb User : 杨俊明
[VHDL-FPGA-Verilog] AESzuihou DL : 0: 在赛灵思软件ISE上实现的ＡＥＳ加解密算法，并且在ＭＯＤＥＬＳＩＭ上仿真。希望对你有所帮助-The Xilinx software ISE AES encryption and decryption algorithms, and simulation MODELSIM on. I hope for your help
Date : 2025-12-15 Size : 79kb User : 杨俊明
[VHDL-FPGA-Verilog] NOIS-II_AES DL : 0: 基于NOIS II的AES加解密系统完整的工程文件 -NOIS II-based AES encryption and decryption of a complete project file system
Date : 2025-12-15 Size : 6.42mb User : 于洋
[VHDL-FPGA-Verilog] AES DL : 0: AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
Date : 2025-12-15 Size : 16kb User : 郑雪松
[VHDL-FPGA-Verilog] RSA DL : 0: 基于FPGA的RSA加解密系统，通过FPGA验证代码为Verilog,开发板为DE2-115-RSA encryption and decryption system based on FPGA, through the FPGA verification code for the Verilog development board, DE2-115
Date : 2025-12-15 Size : 70kb User : 李刚
[VHDL-FPGA-Verilog] Twofish DL : 0: 基于FPGA的Twofish加解密系统，通过FPGA验证代码为Verilog,开发板为DE2-115-Twofish encryption and decryption system based on FPGA, through the FPGA verification code for the Verilog development board, DE2-115
Date : 2025-12-15 Size : 43kb User : 李刚
[VHDL-FPGA-Verilog] 5760finalproject DL : 0: verilog实现的rsa加解密系统，包括大素数生成算法，包含测试文件。-rsa encryption system using verilog, including large prime number generation algorithms, including test file.
Date : 2025-12-15 Size : 1.54mb User : Rain
[VHDL-FPGA-Verilog] 各种密码算法的FPGA实现情况 DL : 0: 各种密码算法的FPGA实现情况 1.AES算法FPGA实现分析 2.DES加密算法的高速FPGA实现 3.RSA加解密运算的FPGA硬件实现研究(FPGA implementation of various cryptographic algorithms)
Date : 2025-12-15 Size : 17.08mb User : wsf-jv