Twofish encryption and decryption system based on FPGA, through the FPGA verification code for the Verilog development board, DE2-115

第5章 基于FPGA的Twofish加解密系统\adder01.vhd
.................................\adder32.do
.................................\adder32.vhd
.................................\ciphertext.do
.................................\ciphertext.vhd
.................................\cleartext.do
.................................\cleartext.vhd
.................................\cntr.do
.................................\cntr.vhd
.................................\control.do
.................................\control.vhd
.................................\core.do
.................................\core.mpf
.................................\core.vhd
.................................\corede.do
.................................\coreen.do
.................................\h_fctn.do
.................................\h_fctn.vhd
.................................\keymodule.do
.................................\keymodule.vhd
.................................\little_endian
.................................\little_endian.do
.................................\little_endian_converter.vhd
.................................\mds.do
.................................\mds.vhd
.................................\modifiedf.do
.................................\modifiedF.vhd
.................................\mux_2x32.vhd
.................................\mux_2x64.vhd
.................................\opselect.do
.................................\opselect.vhd
.................................\perm_q0.do
.................................\Perm_q0.vhd
.................................\Perm_q1.vhd
.................................\pht.do
.................................\pht.vhd
.................................\reg01.vhd
.................................\reg128.vhd
.................................\reg32.vhd
.................................\rol1_32.vhd
.................................\rol8_32.vhd
.................................\rol9_32.vhd
.................................\ror1_32.vhd
.................................\rsmatrix.do
.................................\rsmatrix.vhd
.................................\sub_opselect.do
.................................\sub_opselect.vhd
.................................\s_boxes.do
.................................\s_boxes.vhd
.................................\testbench_twofish.vhd
.................................\twofishen.inp
.................................\twofishen.out
.................................\xor_2x1.vhd
.................................\xor_2x32.vhd
.................................\xor_2x4.vhd
.................................\xor_3x1.vhd
.................................\xor_3x4.vhd
.................................\xor_4x1.vhd
.................................\xor_4x8.vhd
.................................\xor_8x1.vhd
.................................\xor_8x8.vhd
第5章 基于FPGA的Twofish加解密系统

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