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码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.
Date : 2025-12-14 Size : 1kb User : cc

GPS接收机相关器中关于积分清零模块、历元计数模块、时钟模块、以及整个相关器-accumulator、epoch counter、time base、gps baseband
Date : 2025-12-14 Size : 8kb User : lichao
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