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[USB develop] USBDesignBook DL : 0: usb设计资料大全，包含源代码，USB设计图纸，电路连接等，内容很全！-usb Daquan design information, including source code, USB design drawings, circuit connections, as is all!
Date : 2025-12-26 Size : 3.69mb User : 万鹏
[USB develop] Usb_RTL(VHDL_Verilog) DL : 0: USBRTL电路的VHDL和Verilog代码-USBRTL Circuit VHDL and Verilog code
Date : 2025-12-26 Size : 262kb User : 戴鹏
[USB develop] usbvhdl DL : 0: usb 代码用VHDL编写方便初学者使用学习有什么不明白的大家可以回复互相交流-usb using VHDL code to facilitate the preparation of beginners to learn what we do not understand each other can return exchange
Date : 2025-12-26 Size : 3kb User : 和尚
[USB develop] ISP1581veriloghdl DL : 0: usb 接口芯片isp1581 程序，调试过了，好使的-usb interface chip isp1581 procedures, after debugging, so that the
Date : 2025-12-26 Size : 612kb User : cj
[USB develop] usb DL : 0: 实现了USB接口。介绍了如何使用VERILOG语言实现USB的程序设计。-Realize the USB interface. Introduce how to use the Verilog language programming USB realize.
Date : 2025-12-26 Size : 137kb User : xiexiao
[USB develop] usbfree_core DL : 0: 完整的usb freecore，全部用verilog编写-Complete usb freecore, all prepared with Verilog
Date : 2025-12-26 Size : 59kb User : 王天
[USB develop] USB DL : 0: 这个工程是基于FPGA与Philips的D12 USbB 1.1的完整设计，包括VHDL驱动和主机应用程序及驱动-The project is based on FPGA and Philips of the D12 USbB 1.1 complete design, including VHDL-driven and mainframe applications and drivers
Date : 2025-12-26 Size : 2.62mb User : Phirix Shaw
[USB develop] USB DL : 0: fpga设计的usb接口源程序，欢迎指导-FPGA design usb interface source code, welcomed the guidance of
Date : 2025-12-26 Size : 137kb User : 陈楠
[USB develop] ISP1301[1] DL : 0: USB and OTG ISP1301 Spec. Thank!
Date : 2025-12-26 Size : 179kb User : Teo Hsieh
[USB develop] cmos_fifo_usb DL : 0: cmos数据到fifo再到usb的fifo部分程序(68013a)-cmos data to fifo the fifo to the usb part of the procedures (68013a)
Date : 2025-12-26 Size : 155kb User :
[USB develop] usb_phy DL : 0: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Date : 2025-12-26 Size : 11kb User : 颜新卉
[USB develop] usb1_funct DL : 0: usb设备端源代码，包括测试平台和文档。 -usb device client source code, including test platform and documents.
Date : 2025-12-26 Size : 59kb User : xiaojian
[USB develop] usb DL : 0: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD
Date : 2025-12-26 Size : 4.51mb User : 李华
[USB develop] usb20_ipcore_usb_funct DL : 0: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Date : 2025-12-26 Size : 204kb User : road
[USB develop] USB DL : 0: USB 设计（包括一个参考设计，和标准U盘）-USB design (including a reference design, and standards for U disk)
Date : 2025-12-26 Size : 534kb User : zhangsan
[USB develop] USB2.0FPGAEXAMPLES DL : 0: 用于USB20芯片CY7C68013和FPGA之间的通信-comunication between USB and FPGA
Date : 2025-12-26 Size : 2.72mb User : 熊小姐
[USB develop] 2004-02-29_USB_Das_Control_System_dip DL : 0: USB的驱动程序可以方便的使用已经通过验证-USB driver can easily use has been validated
Date : 2025-12-26 Size : 138kb User : sunjia
[USB develop] usb DL : 0: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Date : 2025-12-26 Size : 6kb User : polito
[USB develop] USBblaster DL : 0: FPGA的USB应用电路，已经成功通过测试，可以量产。-Application of FPGA circuit of the USB has been successfully tested, can be mass production.
Date : 2025-12-26 Size : 97kb User : 凌虎
[USB develop] USB-1.1-IP-CORE-VHDL DL : 0: USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
Date : 2025-12-26 Size : 416kb User : sxhfjgl010

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