Search - vhdl delay

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[Communication-Mobile] Mean_64 DL : 0: 原创代码，采用VHDL实现的64点均值滤波。实验测试过，效果良好。可轻松修改成任意点数均值滤波。采用了多点滑动运算，减小了输出延时，最大为3个时钟延迟。可用于AD采样后的滤波处理。-Original code, the use of VHDL to achieve the 64 point mean filter. Experiment tested the results were very good. Can be easily modified into arbitrary point mean filter. Use of multi-point sliding computation, reduces the output delay, a maximum of three clock delay. AD sampling can be used to deal with post-filtering.
Date : 2026-01-10 Size : 2kb User : M