Search - VHDL fifo

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[Communication-Mobile] uart DL : 0: 这个是UART的控制器，已经跑通过，分4个模块，波特率生成、发送、接收和fifo,可供初学者参考-This is the UART controller, has been run through, sub-4 module, baud rate generating, sending, receiving and fifo, for beginners reference
Date : 2026-01-02 Size : 3kb User : duan
[Communication-Mobile] fifo DL : 0: fifo buffer in vhdl, first in first out in vhdl, vhdl code
Date : 2026-01-02 Size : 1kb User : sgma
[Communication-Mobile] xfft_v3_2_pipe_64 DL : 0: vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
Date : 2026-01-02 Size : 2.97mb User : xy