Search - fifo-ram

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[Other] verilog_fifo DL : 0: verilog fifo
Date : 2025-12-23 Size : 4kb User : 王新
[Other] FIFORAM DL : 0: FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
Date : 2025-12-23 Size : 324kb User : SMILE
[Other] maxii_sch DL : 0: 采用EPM570作为核心，外接FIFO，RAM。可进行数据采集，采用60M时钟的ADC ADS830E。ADC前端电路需要改为差分输入方式以减小电路噪声。该电路经过实际检验可以使用，需要将JTAG电阻改为220以下或者短接。-EPM570 used as a core, external FIFO, RAM. Can be a data collection, using 60M clock ADC ADS830E. ADC front-end circuit differential input methods need to be changed to reduce the circuit noise. The circuit is subject to practical tests can be used needs to be changed to 220 the following JTAG resistance or shorted.
Date : 2025-12-23 Size : 14kb User : zhuyi
[Other] uart DL : 0: 此文档为C51单片机串口通讯学习程序（中断+FIFO)-This document is for the C51 microcontroller serial communication learning process (interrupted+ FIFO)
Date : 2025-12-23 Size : 6kb User :