Search - accumulator

Search - accumulator - List

[Other] dds DL : 0: FPGA实现直接数字信号源.一个相位累加器的设计-FPGA realization of direct digital signal source. A phase accumulator design
Date : 2025-12-14 Size : 5kb User : 马彩青
[Other] dds DL : 0: 累加器的描述，已经通过实验成功，可以用于波形发生器中-Accumulator description has been successful through experiments, can be used in the waveform generator
Date : 2025-12-14 Size : 2kb User : 刘明明
[Other] b DL : 0: A high-speed variable phase accumulator for an ADPLL architecture
Date : 2025-12-14 Size : 281kb User : bc
[Other] Sample3 DL : 0: 輔以java語法做四則運算，用累加器的觀念，作數字的總和。-Supplemented with java syntax to do four operations, using the concept of accumulator for sum of the figures.
Date : 2025-12-14 Size : 2kb User : james
[Other] Accumulator DL : 0: 计算机组成原理实验简单的加法器程序。仅供大家参考。-Computer Composition Theory Experiment a simple adder program. Only for your reference.
Date : 2025-12-14 Size : 137kb User : 于洪宇
[Other] cpu DL : 0: 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7), the program counter 8) address multiplexer
Date : 2025-12-14 Size : 430kb User : liuying
[Other] Private-Sub-Command1 DL : 0: 数字累加器，可键盘输入，也可鼠标操作。是初学者的练习，不要见笑了-Digital accumulator keyboard input, but also the mouse. A beginner' s exercise, do not laugh at the
Date : 2025-12-14 Size : 2kb User : cuiwei
[Other] event-structure DL : 0: 利用labview的事件结构，实现累加器的功能。-Labview using the event structure to achieve the accumulator function.
Date : 2025-12-14 Size : 9kb User : meilin
[Other] 1286857427_22104_FT38772_at DL : 0: Accumulator code is source code for simulating accumulator.
Date : 2025-12-14 Size : 43kb User : aa
[Other] Basic-sequential-logic DL : 0: 用Verilog语言实现D触发器、累加器的功能-D flip-flop, the function of the accumulator using Verilog language
Date : 2025-12-14 Size : 40kb User : 李炜
[Other] accumulator DL : 0: accumulator max plus
Date : 2025-12-14 Size : 5kb User : rls1324
[Other] ds18B20 DL : 0: 一、DS18B20 的主要特性（1）适应电压范围更宽，电压范围：3.0～5.5V，在寄生电源方式下可由数据线供电（2）独特的单线接口方式，DS18B20 在与微处理器连接时仅需要一条口线即可实现微处理器与 DS18B20 的双向通讯（3）DS18B20 支持多点组网功能，多个 DS18B20 可以并联在唯一的三线上，实现组网多点测温-FEATURES Unique 1-Wire ® interface requires only one port pin for communication Provides unique 64-bit serial number to battery packs Eliminates thermistors by sensing battery temperature on-chip On-board A/D converter allows monitoring of battery voltage for end-of-charge and end-of-discharge determination On-board integrated current accumulator facilitates fuel gauging Elapsed time meter in binary format
Date : 2025-12-14 Size : 1.04mb User : lei金
[Other] my_multiplier DL : 0: 一个VHDL编的简单乘法器，基本原理设计如下图所示: 将两个操作数分别以串行和并行模式输入到乘法器的输入端, 用串行输入操作数的每一位依次去乘并行输入的操作数, 每次的结果称之为部分积, 将每次相乘得到的部分积加到累加器里, 形成部分和, 部分和在与下一个部分积相加前要进行移位操作。-A simple multiplier VHDL series, the basic principles of design as follows: two operands, respectively, serial and parallel mode to the input terminal of the multiplier, with every serial input operands in parallel in order to multiply the input operands, the result of each partial product is called, the partial products obtained by multiplying each time to the accumulator, the forming portion, and, prior to the addition portion and with the next partial product is shifted to .
Date : 2025-12-14 Size : 1kb User : Justin
[Other] accumulator DL : 0: 一个简单的加法器实现程序，已验证，使用的是Verilog HDL编写，适合初学者入门学习-A simple adder procedures, verified, using Verilog HDL prepared, for beginners to learn
Date : 2025-12-14 Size : 1kb User : 金贝贝
[Other] 用verilog编写的sigma-delta adc例子 DL : 0: 累加器实现艾哈空间哈卡哈尽快啊哈卡哈卡快捷回复哈哈哈看(Accumulator implementation)
Date : 2025-12-14 Size : 4kb User : 西伯利亚牛
[Other] addcontrolk DL : 0: 累加器，适用于数字频率合成器的时钟模块，输出一个阶梯状的信号(Accumulator is suitable for the clock module of the digital frequency synthesizer, and outputs a ladder like signal.)
Date : 2025-12-14 Size : 2kb User : 大piepie
[Other] 流水线乘法累加器设计 DL : 0: 调用寄存器LPM,流水线加法器LPM,流水线乘法器LPM等模块实现一个8位流水线乘法累加器。(Call a register LPM, pipelined adder LPM, pipeline multiplier LPM and other modules to achieve a 8 bit pipelined multiplication accumulator.)
Date : 2025-12-14 Size : 939kb User : 墨染静然