Description: The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| 异步FIFO\bin2gray.v | 328 | 2020-10-19
|
| 异步FIFO\dual_ram.v | 638 | 2020-10-19
|
| 异步FIFO\fifo_tb.v | 1250 | 2020-10-19
|
| 异步FIFO\file.list | 81 | 2020-10-21
|
| 异步FIFO\makefile | 229 | 2020-10-19
|
| 异步FIFO\read_con.v | 654 | 2020-10-19
|
| 异步FIFO\syn.v | 816 | 2020-10-19
|
| 异步FIFO\top.v | 1531 | 2020-10-19
|
| 异步FIFO\write_con.v | 713 | 2020-10-19
|
| 异步FIFO | 0 | 2020-11-10 |
Download