Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: BPSK Download
 Description: Firstly, the filter coefficients are obtained by simulation with the theory of matlab. Then the program is written in Verilog language under ISE environment. Waveform simulation and quotation mark grabbing are carried out through Modelsim and ChipScope, so as to improve the efficiency of debugging. The parameters of up-down converter are controlled by sending instructions from mobile phone.
 Downloaders recently: [More information of uploader 财哥在此]
 To Search:
File list (Check if you may need any files):
FilenameSizeDate
BPSK\aaa.m 59 2019-05-07
BPSK\BPSK.m 3519 2019-06-17
BPSK\BPSK_Signal.cmd_log 317 2019-05-06
BPSK\BPSK_Signal.v 1922 2019-05-08
BPSK\BSK.coe 845 2019-05-08
BPSK\B_H.coe 855 2019-05-08
BPSK\B_L.coe 845 2019-05-08
BPSK\CXD301.ucf 8465 2019-05-07
BPSK\FIR_BPSK.mif 1148 2019-05-07
BPSK\FIR_BPSKCOEFF_auto0_0.mif 126 2019-05-07
BPSK\FIR_BPSKCOEFF_auto0_1.mif 126 2019-05-07
BPSK\FIR_BPSKCOEFF_auto0_2.mif 126 2019-05-07
BPSK\FIR_BPSKCOEFF_auto0_3.mif 126 2019-05-07
BPSK\FIR_BPSKCOEFF_auto0_4.mif 126 2019-05-07
BPSK\FIR_BPSKCOEFF_auto0_5.mif 126 2019-05-07
BPSK\FIR_BPSKfilt_decode_rom.mif 85 2019-05-07
BPSK\FIR_High.mif 854 2019-05-06
BPSK\FIR_HighCOEFF_auto0_0.mif 126 2019-05-06
BPSK\FIR_HighCOEFF_auto0_1.mif 126 2019-05-06
BPSK\FIR_HighCOEFF_auto0_2.mif 126 2019-05-06
BPSK\FIR_HighCOEFF_auto0_3.mif 126 2019-05-06
BPSK\FIR_Highfilt_decode_rom.mif 85 2019-05-06
BPSK\FIR_Low.mif 1148 2019-05-07
BPSK\FIR_LowCOEFF_auto0_0.mif 126 2019-05-07
BPSK\FIR_LowCOEFF_auto0_1.mif 126 2019-05-07
BPSK\FIR_LowCOEFF_auto0_2.mif 126 2019-05-07
BPSK\FIR_LowCOEFF_auto0_3.mif 126 2019-05-07
BPSK\FIR_LowCOEFF_auto0_4.mif 126 2019-05-07
BPSK\FIR_LowCOEFF_auto0_5.mif 126 2019-05-07
BPSK\FIR_Lowfilt_decode_rom.mif 85 2019-05-07
BPSK\integrated_design.bgn 8010 2019-06-17
BPSK\integrated_design.bit 464872 2019-06-17
BPSK\Integrated_Design.bld 1509 2019-06-17
BPSK\Integrated_Design.cmd_log 889 2019-06-17
BPSK\integrated_design.drc 1186 2019-06-17
BPSK\Integrated_Design.lso 6 2019-06-17
BPSK\Integrated_Design.ncd 597345 2019-06-17
BPSK\Integrated_Design.ngc 79380 2019-06-17
BPSK\Integrated_Design.ngd 1639608 2019-06-17
BPSK\Integrated_Design.ngr 73164 2019-06-17
BPSK\Integrated_Design.pad 12304 2019-06-17
BPSK\Integrated_Design.par 12519 2019-06-17
BPSK\Integrated_Design.pcf 43002 2019-06-17
BPSK\Integrated_Design.prj 417 2019-06-17
BPSK\Integrated_Design.ptwx 18998 2019-06-17
BPSK\Integrated_Design.stx 0 2019-06-17
BPSK\Integrated_Design.syr 40184 2019-06-17
BPSK\Integrated_Design.twr 140129 2019-06-17
BPSK\Integrated_Design.twx 164515 2019-06-17
BPSK\Integrated_Design.unroutes 161 2019-06-17
BPSK\Integrated_Design.ut 553 2019-06-17
BPSK\Integrated_Design.v 2437 2019-06-17
BPSK\Integrated_Design.xpi 46 2019-06-17
BPSK\Integrated_Design.xst 1123 2019-06-17
BPSK\Integrated_Design_bitgen.xwbt 289 2019-06-17
BPSK\Integrated_Design_cs.blc 1348 2019-06-17
BPSK\Integrated_Design_cs.ngc 1155488 2019-06-17
BPSK\Integrated_Design_guide.ncd 597345 2019-06-17
BPSK\Integrated_Design_map.map 8923 2019-06-17
BPSK\Integrated_Design_map.mrp 61786 2019-06-17
BPSK\Integrated_Design_map.ncd 338642 2019-06-17
BPSK\Integrated_Design_map.ngm 3050987 2019-06-17
BPSK\Integrated_Design_map.xrpt 34176 2019-06-17
BPSK\Integrated_Design_ngdbuild.xrpt 24466 2019-06-17
BPSK\Integrated_Design_pad.csv 12336 2019-06-17
BPSK\Integrated_Design_pad.txt 51800 2019-06-17
BPSK\Integrated_Design_par.xrpt 144840 2019-06-17
BPSK\Integrated_Design_summary.html 3551 2019-06-17
BPSK\Integrated_Design_summary.xml 408 2019-06-17
BPSK\Integrated_Design_usage.xml 111229 2019-06-17
BPSK\Integrated_Design_xst.xrpt 15861 2019-06-17
BPSK\ipcore_dir\.lso 19 2019-05-07
BPSK\ipcore_dir\coregen.cgp 238 2019-05-07
BPSK\ipcore_dir\create_FIR_BPSK.tcl 1261 2019-05-07
BPSK\ipcore_dir\create_FIR_High.tcl 1261 2019-05-06
BPSK\ipcore_dir\create_FIR_Low.tcl 1260 2019-05-06
BPSK\ipcore_dir\create_My_Clk.tcl 1255 2019-05-06
BPSK\ipcore_dir\create_Sin_1500K.tcl 1262 2019-05-06
BPSK\ipcore_dir\create_Sin_1M.tcl 1259 2019-05-07
BPSK\ipcore_dir\create_Sin_2M.tcl 1259 2019-05-07
BPSK\ipcore_dir\create_Sin_500K.tcl 1261 2019-05-06
BPSK\ipcore_dir\edit_FIR_BPSK.tcl 1124 2019-05-07
BPSK\ipcore_dir\edit_FIR_High.tcl 1124 2019-05-07
BPSK\ipcore_dir\edit_FIR_Low.tcl 1123 2019-05-07
BPSK\ipcore_dir\edit_My_Clk.tcl 1122 2019-05-08
BPSK\ipcore_dir\edit_Sin_1500K.tcl 1125 2019-05-07
BPSK\ipcore_dir\edit_Sin_500K.tcl 1124 2019-05-20
BPSK\ipcore_dir\FIR_BPSK.asy 535 2019-05-07
BPSK\ipcore_dir\FIR_BPSK.gise 1364 2019-06-17
BPSK\ipcore_dir\FIR_BPSK.mif 1148 2019-05-07
BPSK\ipcore_dir\FIR_BPSK.ncf 0 2019-06-17
BPSK\ipcore_dir\FIR_BPSK.ngc 199415 2019-05-07
BPSK\ipcore_dir\FIR_BPSK.sym 1532 2019-05-07
BPSK\ipcore_dir\FIR_BPSK.v 260527 2019-05-07
BPSK\ipcore_dir\FIR_BPSK.veo 4705 2019-05-07
BPSK\ipcore_dir\FIR_BPSK.xco 3110 2019-05-07
BPSK\ipcore_dir\FIR_BPSK.xise 4903 2019-05-07
BPSK\ipcore_dir\FIR_BPSKCOEFF_auto0_0.mif 126 2019-05-07
BPSK\ipcore_dir\FIR_BPSKCOEFF_auto0_1.mif 126 2019-05-07
BPSK\ipcore_dir\FIR_BPSKCOEFF_auto0_2.mif 126 2019-05-07

CodeBus www.codebus.net