- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 334kb
- Update:
- 2019-05-03
- Downloads:
- 1 Times
- Uploaded by:
- 羊羊驼
Description: Design a 1MHz FIR low pass filter.
Requirements:
(1) clock signal frequency 16MHz;
(2) input signal bit width of 8bits, symbol rate of 16MHz
Requirements in Matlab FIR filter floating-point and fixed-point simulation, and determine the FIR filter tap coefficient
(4) write the test simulation program.
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| 滤波器实验报告.docx | 364487 | 2019-04-28 |
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