- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 3kb
- Update:
- 2018-05-01
- Downloads:
- 0 Times
- Uploaded by:
- 林林明
Description: The module of FIFO is modified by using synchronous FIFO, which contains some design skills and the least latency.
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| fifo.v | 47702 | 2018-03-21 |
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