- Category:
- VHDL-FPGA-Verilog
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-
- File Size:
- 244kb
- Update:
- 2018-04-21
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- Uploaded by:
- 硅渣渣
Description: Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_done command is sent. This command lets us judge whether the last word is finished or if the FAM will be sent after completion. The next command
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| Filename | Size | Date |
|---|
| FPGA_flash设计.docx | 253853 | 2017-07-09 |
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