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Title: risc_spm_v14 Download
 Description: Using Altera CycloneIV to implement a streamlined instruction set CPU in Verilog language
 Downloaders recently: [More information of uploader LucienJ]
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File list (Check if you may need any files): 
FilenameSizeDate
risc_spm 0  2018-01-22

risc_spm\code 0  2018-01-22

risc_spm\code\risc_spm_zx1801 0  2018-01-23

risc_spm\code\risc_spm_zx1801\alu_model.v 416  2018-01-22

risc_spm\code\risc_spm_zx1801\alu_model.v.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\controller.v 5424  2018-01-23

risc_spm\code\risc_spm_zx1801\controller.v.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\db 0  2018-01-23

risc_spm\code\risc_spm_zx1801\db\altsyncram_53m1.tdf 12783  2018-01-23

risc_spm\code\risc_spm_zx1801\db\logic_util_heursitic.dat 0  2018-01-23

risc_spm\code\risc_spm_zx1801\db\prev_cmp_risc_spm_zx1801.qmsg 80921  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(0).cnf.cdb 1933  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(0).cnf.hdb 1256  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(1).cnf.cdb 16637  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(1).cnf.hdb 2596  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(10).cnf.cdb 1600  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(10).cnf.hdb 770  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(11).cnf.cdb 1988  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(11).cnf.hdb 772  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(2).cnf.cdb 5465  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(2).cnf.hdb 2130  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(3).cnf.cdb 1693  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(3).cnf.hdb 826  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(4).cnf.cdb 2151  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(4).cnf.hdb 1165  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(5).cnf.cdb 1693  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(5).cnf.hdb 953  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(6).cnf.cdb 2334  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(6).cnf.hdb 915  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(7).cnf.cdb 863  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(7).cnf.hdb 624  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(8).cnf.cdb 3210  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(8).cnf.hdb 1517  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(9).cnf.cdb 1558  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.(9).cnf.hdb 896  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.cbx.xml 238  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.cmp.rdb 8896  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.cmp_merge.kpt 223  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.db_info 152  2018-01-22

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.hier_info 20962  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.hif 11632  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.lpc.html 7056  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.lpc.rdb 647  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.lpc.txt 4968  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map.bpm 647  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map.cdb 1378  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map.hdb 16449  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map.kpt 2144  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map.logdb 4  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map.qmsg 79619  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map_bb.cdb 1097  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map_bb.hdb 15529  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.map_bb.logdb 4  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.pre_map.cdb 38999  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.pre_map.hdb 21543  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.ram0_memory_e411fb78.hdl.mif 4631  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.rtlv.hdb 21334  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.rtlv_sg.cdb 32900  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.rtlv_sg_swap.cdb 3146  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.sgdiff.cdb 1044  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.sgdiff.hdb 25864  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.sld_design_entry.sci 211  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.sld_design_entry_dsc.sci 211  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.smart_action.txt 5  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.smp_dump.txt 464  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.syn_hier_info 0  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.tis_db_list.ddb 187  2018-01-23

risc_spm\code\risc_spm_zx1801\db\risc_spm_zx1801.tmw_info 67  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db 0  2018-01-22

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions 0  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.db_info 152  2018-01-22

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.root_partition.map.cdb 1193  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.root_partition.map.dpi 1484  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.root_partition.map.hbdb.cdb 618  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.root_partition.map.hbdb.hb_info 46  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.root_partition.map.hbdb.hdb 16090  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.root_partition.map.hbdb.sig 31  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.root_partition.map.hdb 16412  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\compiled_partitions\risc_spm_zx1801.root_partition.map.kpt 2149  2018-01-23

risc_spm\code\risc_spm_zx1801\incremental_db\README 653  2018-01-22

risc_spm\code\risc_spm_zx1801\init_prg1.txt 268  2018-01-23

risc_spm\code\risc_spm_zx1801\init_prg1.txt.bak 0  2018-01-23

risc_spm\code\risc_spm_zx1801\init_ram.txt 105  2018-01-22

risc_spm\code\risc_spm_zx1801\init_ram.txt.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\jf31.tcl 7909  2015-08-10

risc_spm\code\risc_spm_zx1801\memory.v 519  2018-01-23

risc_spm\code\risc_spm_zx1801\memory.v.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\mux1.v 404  2018-01-22

risc_spm\code\risc_spm_zx1801\mux1.v.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\mux2.v 364  2018-01-22

risc_spm\code\risc_spm_zx1801\mux2.v.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\pc_reg.v 350  2018-01-22

risc_spm\code\risc_spm_zx1801\pc_reg.v.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\processor.v 2240  2018-01-22

risc_spm\code\risc_spm_zx1801\processor.v.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\reg1.v 252  2018-01-22

risc_spm\code\risc_spm_zx1801\reg1.v.bak 131  2018-01-22

risc_spm\code\risc_spm_zx1801\reg8.v 263  2018-01-22

risc_spm\code\risc_spm_zx1801\reg8.v.bak 0  2018-01-22

risc_spm\code\risc_spm_zx1801\risc_spm_zx1801.done 26  2018-01-23

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