- Category:
- VHDL-FPGA-Verilog
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-
- File Size:
- 1kb
- Update:
- 2018-01-04
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- Uploaded by:
- 殷雪凤
Description: Through the SPI interface to a 16 bit length 8 configuration register assignment. Width 16 digits represent the information stored for 16, length 8, is the representative of the register depth is 8.
When the first bit of data is entered, a counter, count, is defined to determine the number of data received at the present time. When eighth bits are received, the 6 bits are the addresses, the first two bits are used for judgement, 10 is the read operation, 11 is the write operation, and it still needs to count after entering the read and write operation, so as to decide when to read or write, and when count=24 is read and write.
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| Filename | Size | Date |
|---|
| spi\spi.v | 1861 | 2018-01-03
|
| spi\tb_spi.v | 1486 | 2017-12-04
|
| spi | 0 | 2018-01-03 |
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