- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 32kb
- Update:
- 2017-12-18
- Downloads:
- 0 Times
- Uploaded by:
- 浩林
Description: For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| alu.v | 3130 | 2017-12-04
|
| Asynchronous_D_FF.v | 478 | 2017-11-13
|
| Counter8.v | 637 | 2017-11-20
|
| decoder.bit | 3825892 | 2017-10-23
|
| decoder.v | 1298 | 2017-10-23
|
| decoder_tb.v | 1116 | 2017-10-23
|
| decoder_xdc.xdc | 1426 | 2017-10-23
|
| display7.bit | 3825893 | 2017-10-23
|
| display7.v | 1540 | 2017-10-23
|
| display7_tb.v | 1054 | 2017-10-23
|
| display7_xdc.xdc | 1210 | 2017-10-23
|
| Divider.v | 4998 | 2017-11-20
|
| encoder83.bit | 3825894 | 2017-10-23
|
| encoder83.v | 823 | 2017-10-23
|
| encoder83_Pri.bit | 3825898 | 2017-10-23
|
| encoder83_Pri.v | 1439 | 2017-10-23
|
| encoder83_Pri_tb.v | 1172 | 2017-10-23
|
| encoder83_Pri_xdc.xdc | 1402 | 2017-10-23
|
| encoder83_tb.v | 980 | 2017-10-23
|
| encoder83_xdc.xdc | 1210 | 2017-10-23
|
| JK_FF.v | 825 | 2017-11-13
|
| Pcreg.v | 814 | 2017-11-27
|
| ram.v | 1588 | 2017-11-27
|
| ram2.v | 634 | 2017-11-27
|
| Regfiles.v | 2990 | 2017-11-27
|
| Selector.v | 2294 | 2017-11-27
|
| Synchronous_D_FF.v | 443 | 2017-11-13 |
Download