- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 7kb
- Update:
- 2017-12-11
- Downloads:
- 0 Times
- Uploaded by:
- 浩林
Description: The implementation of divider, alu, ram etc. in verilog
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| alu.v | 3130 | 2017-12-04
|
| Asynchronous_D_FF.v | 478 | 2017-11-13
|
| Counter8.v | 637 | 2017-11-20
|
| Decoder.v | 2884 | 2017-11-27
|
| display7.v | 1094 | 2017-11-19
|
| Divider.v | 4998 | 2017-11-20
|
| JK_FF.v | 825 | 2017-11-13
|
| Pcreg.v | 814 | 2017-11-27
|
| ram.v | 1588 | 2017-11-27
|
| ram2.v | 634 | 2017-11-27
|
| Regfiles.v | 2990 | 2017-11-27
|
| Selector.v | 2294 | 2017-11-27
|
| Synchronous_D_FF.v | 443 | 2017-11-13 |
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