- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 500kb
- Update:
- 2017-12-08
- Downloads:
- 0 Times
- Uploaded by:
- 杨凯
Description: The receiver tests the input signal,
Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted
And output the generated data
The compressed package includes the Verilog code, the testbench code
Matlab simulation code
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