- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 20kb
- Update:
- 2017-09-21
- Downloads:
- 0 Times
- Uploaded by:
- 高军
Description: Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure;
Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry
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File list (Check if you may need any files):
ddr_sdram\ddr_dcm.vhd
ddr_sdram\ddr_sdr.vhd
ddr_sdram\ddr_sdr_conf_pkg.vhd
ddr_sdram\mt46v16m16.vhd
ddr_sdram\reset.vhd
ddr_sdram\tb.vhd
ddr_sdram\user_if.vhd
ddr_sdram
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