Xilinx 的I2C工程
................\I2C
................\...\I2C.dhp
................\...\I2C.npl
................\...\__projnav
................\...\.........\I2C.gfl
................\...\.........\I2C_flowplus.gfl
................\...\.........\coregen.rsp
................\...\.........\i2c_master_bit_ctrl.xst
................\...\.........\i2c_master_byte_ctrl.xst
................\...\.........\i2c_master_top.xst
................\...\.........\runXst_tcl.rsp
................\...\.........\xst_sprjTOstx_tcl.rsp
................\...\__projnav.log
................\...\automake.log
................\...\coregen.log
................\...\coregen.prj
................\...\i2c_master_bit_ctrl.cmd_log
................\...\i2c_master_bit_ctrl.lso
................\...\i2c_master_bit_ctrl.ngc
................\...\i2c_master_bit_ctrl.ngr
................\...\i2c_master_bit_ctrl.prj
................\...\i2c_master_bit_ctrl.stx
................\...\i2c_master_bit_ctrl.syr
................\...\i2c_master_bit_ctrl.v
................\...\i2c_master_bit_ctrl_vhdl.prj
................\...\i2c_master_byte_ctrl.cmd_log
................\...\i2c_master_byte_ctrl.lso
................\...\i2c_master_byte_ctrl.ngc
................\...\i2c_master_byte_ctrl.ngr
................\...\i2c_master_byte_ctrl.prj
................\...\i2c_master_byte_ctrl.stx
................\...\i2c_master_byte_ctrl.syr
................\...\i2c_master_byte_ctrl.v
................\...\i2c_master_byte_ctrl_vhdl.prj
................\...\i2c_master_defines.v
................\...\i2c_master_top.cmd_log
................\...\i2c_master_top.lso
................\...\i2c_master_top.ngc
................\...\i2c_master_top.ngr
................\...\i2c_master_top.prj
................\...\i2c_master_top.stx
................\...\i2c_master_top.syr
................\...\i2c_master_top.v
................\...\i2c_master_top_vhdl.prj
................\...\i2c_slave_model.fdo
................\...\i2c_slave_model.ndo
................\...\i2c_slave_model.udo
................\...\i2c_slave_model.v
................\...\prjname.lso
................\...\timescale.v
................\...\transcript
................\...\tst_bench_top.v
................\...\wb_master_model.v
................\...\work
................\...\....\_info
................\...\....\glbl
................\...\....\....\_primary.dat
................\...\....\....\_primary.vhd
................\...\....\....\verilog.asm
................\...\....\i2c_slave_model
................\...\....\...............\_primary.dat
................\...\....\...............\_primary.vhd
................\...\....\...............\verilog.asm
................\...\xst
................\...\...\work
................\...\...\....\hdllib.ref
................\...\...\....\vlg07
................\...\...\....\.....\i2c_master_bit_ctrl.bin
................\...\...\....\vlg5C
................\...\...\....\.....\i2c_master_byte_ctrl.bin
................\...\...\....\vlg67
................\...\...\....\.....\i2c_master_top.bin