Description: This folder inside the pic10 CPU is to achieve all the verilog code and the corresponding test script code, of course, there are some modules in quartus directly edit the waveform test, so there is no response to the test script file.
Tri_state_port test has not yet completed, test_pic10_status_reg.vt and test_pic10_tri_state_port2.vt are not complete test tasks
There are three documents:
PIC10_RISC_Design.pdf: the original (verilog code basically the original, on a part of the improvement), this article is written very well
PIC10F200_ IP core of the realization of single-chip.pdf: The above article combined with their own experimental process of translation and rewriting, for your reference
PIC10F: PIC10 family of microcontrollers
To Search:
File list (Check if you may need any files):
pic10_verilog\PIC10F.pdf
.............\PIC10F200_单片机IP核的实现.pdf
.............\pic10_alu.v
.............\pic10_alu_datapath.v
.............\pic10_alu_mux.v
.............\pic10_controller.v
.............\pic10_cpu.v
.............\pic10_datapath.v
.............\pic10_fsr.v
.............\pic10_gpio_reg.v
.............\pic10_ir.v
.............\pic10_pc.v
.............\pic10_pc_datapath.v
.............\pic10_pc_mux.v
.............\pic10_program_mux.v
.............\pic10_program_store.v
.............\pic10_ram_registers.v
.............\pic10_ram_sfr_datapath.v
.............\pic10_register_address_mux.v
.............\PIC10_RISC_Design.pdf
.............\pic10_sfr_data_mux.v
.............\pic10_stack.v
.............\pic10_status_reg.v
.............\pic10_tris_reg.v
.............\pic10_tri_state_port.v
.............\pic10_w_reg.v
.............\test_pic10_alu.vt
.............\test_pic10_alu_datapath.vt
.............\test_pic10_alu_mux.vt
.............\test_pic10_cpu.vt
.............\test_pic10_ir.vt
.............\test_pic10_pc_datapath.vt
.............\test_pic10_ram_registers.vt
.............\test_pic10_ram_sfr_datapath.vt
.............\test_pic10_stack.vt
.............\test_pic10_status_reg.vt
.............\test_pic10_tri_state_port.vt
.............\test_pic10_tri_state_port2.vt
.............\test_pic10_w_reg.vt
pic10_verilog
Download