Description: Calculator design. Using a field programmable logic device FPGA design, VHDL language based on arithmetic function, and decimal display on the digital tube. Computing part adder, subtraction, multiplier and divider composition. QuartusII using Altera s development software for functional simulation and gives the simulation waveforms, and download to the chamber, with the key switch on the analog input experimental box with digital display decimal calculations. External keys can be done by four binary numbers to add, subtract, multiply, and divide four kinds of computing functions, the result is simple and easy to implement.
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AnJian_1602
...........\AnJian.asm.rpt
...........\AnJian.done
...........\AnJian.fit.rpt
...........\AnJian.fit.smsg
...........\AnJian.fit.summary
...........\AnJian.flow.rpt
...........\AnJian.map.rpt
...........\AnJian.map.summary
...........\AnJian.pin
...........\AnJian.qpf
...........\AnJian.qsf
...........\AnJian.sof
...........\AnJian.sta.rpt
...........\AnJian.sta.summary
...........\AnJian.vhd
...........\AnJian.vhd.bak
...........\AnJian_1602.asm.rpt
...........\AnJian_1602.bsf
...........\AnJian_1602.cdf
...........\AnJian_1602.cmp
...........\AnJian_1602.done
...........\AnJian_1602.fit.rpt
...........\AnJian_1602.fit.smsg
...........\AnJian_1602.fit.summary
...........\AnJian_1602.flow.rpt
...........\AnJian_1602.map.rpt
...........\AnJian_1602.map.summary
...........\AnJian_1602.pin
...........\AnJian_1602.qpf
...........\AnJian_1602.qsf
...........\AnJian_1602.qsf.bak
...........\anJian_1602.qsv.txt
...........\AnJian_1602.sof
...........\AnJian_1602.sta.rpt
...........\AnJian_1602.sta.summary
...........\AnJian_1602.vhd
...........\AnJian_1602.vhd.bak
...........\db
...........\..\AnJian.amm.cdb
...........\..\AnJian.asm.qmsg
...........\..\AnJian.asm.rdb
...........\..\AnJian.asm_labs.ddb
...........\..\AnJian.cbx.xml
...........\..\AnJian.cmp.bpm
...........\..\AnJian.cmp.cdb
...........\..\AnJian.cmp.hdb
...........\..\AnJian.cmp.kpt
...........\..\AnJian.cmp.logdb
...........\..\AnJian.cmp.rdb
...........\..\AnJian.cmp_merge.kpt
...........\..\AnJian.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
...........\..\AnJian.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
...........\..\AnJian.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
...........\..\AnJian.db_info
...........\..\AnJian.fit.qmsg
...........\..\AnJian.hier_info
...........\..\AnJian.hif
...........\..\AnJian.idb.cdb
...........\..\AnJian.lpc.html
...........\..\AnJian.lpc.rdb
...........\..\AnJian.lpc.txt
...........\..\AnJian.map.bpm
...........\..\AnJian.map.cdb
...........\..\AnJian.map.hdb
...........\..\AnJian.map.kpt
...........\..\AnJian.map.logdb
...........\..\AnJian.map.qmsg
...........\..\AnJian.map_bb.cdb
...........\..\AnJian.map_bb.hdb
...........\..\AnJian.map_bb.logdb
...........\..\AnJian.pre_map.cdb
...........\..\AnJian.pre_map.hdb
...........\..\AnJian.rtlv.hdb
...........\..\AnJian.rtlv_sg.cdb
...........\..\AnJian.rtlv_sg_swap.cdb
...........\..\AnJian.sgdiff.cdb
...........\..\AnJian.sgdiff.hdb
...........\..\AnJian.sld_design_entry.sci
...........\..\AnJian.sld_design_entry_dsc.sci
...........\..\AnJian.smart_action.txt
...........\..\AnJian.smp_dump.txt
...........\..\AnJian.sta.qmsg
...........\..\AnJian.sta.rdb
...........\..\AnJian.sta_cmp.8_slow_1200mv_85c.tdb
...........\..\AnJian.syn_hier_info
...........\..\AnJian.tiscmp.fastest_slow_1200mv_0c.ddb
...........\..\AnJian.tiscmp.fastest_slow_1200mv_85c.ddb
...........\..\AnJian.tiscmp.fast_1200mv_0c.ddb
...........\..\AnJian.tiscmp.slow_1200mv_0c.ddb
...........\..\AnJian.tiscmp.slow_1200mv_85c.ddb
...........\..\AnJian.tis_db_list.ddb
...........\..\AnJian_1602.amm.cdb
...........\..\AnJian_1602.asm.qmsg
...........\..\AnJian_1602.asm.rdb
...........\..\AnJian_1602.asm_labs.ddb
...........\..\AnJian_1602.cbx.xml
...........\..\AnJian_1602.cmp.bpm
...........\..\AnJian_1602.cmp.cdb
...........\..\AnJian_1602.cmp.hdb
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