- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 6kb
- Update:
- 2015-12-21
- Downloads:
- 0 Times
- Uploaded by:
- 安迪
Description: VHDL language design electronic clock, and there is a pause function and achieve clear function buttons, and with stopwatch
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电子钟\control.vhd
......\display.vhd
......\HOUR.vhd
......\minute.vhd
......\SECOND.vhd
......\TOP.ucf
......\TOP.vhd
电子钟
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