Description: I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
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File list (Check if you may need any files):
VHDL projects\project4\.lso
.............\........\citac.cmd_log
.............\........\citac.spl
.............\........\citac.sym
.............\........\citac.vhd
.............\........\Dekoder.cmd_log
.............\........\Dekoder.spl
.............\........\Dekoder.sym
.............\........\Dekoder.vhd
.............\........\Dekoder_summary.html
.............\........\delicka.cmd_log
.............\........\delicka.prj
.............\........\delicka.spl
.............\........\delicka.stx
.............\........\delicka.sym
.............\........\delicka.vhd
.............\........\delicka.xst
.............\........\delicka_vhdl.prj
.............\........\iseconfig\Dekoder.xreport
.............\........\.........\projekt4_kizek.projectmgr
.............\........\.........\TOPsheet.xreport
.............\........\pa.fromNetlist.tcl
.............\........\pepExtractor.prj
.............\........\planAhead.ngc2edif.log
.............\........\........._run_1\planAhead.jou
.............\........\...............\planAhead.log
.............\........\...............\planAhead_run.log
.............\........\...............\.rojekt4_kizek.data\constrs_1\designprops.xml
.............\........\...............\...................\.........\fileset.xml
.............\........\...............\...................\.........\usercols.xml
.............\........\...............\...................\runs\impl_1.psg
.............\........\...............\...................\....\runs.xml
.............\........\...............\...................\sources_1\chipscope.xml
.............\........\...............\...................\.........\fileset.xml
.............\........\...............\...................\.........\ports.xml
.............\........\...............\...................\wt\webtalk_pa.xml
.............\........\...............\projekt4_kizek.ppr
.............\........\projekt4_kizek.gise
.............\........\projekt4_kizek.xise
.............\........\sch2HdlBatchFile
.............\........\topsheet.bgn
.............\........\topsheet.bit
.............\........\TOPsheet.bld
.............\........\TOPsheet.cmd_log
.............\........\topsheet.drc
.............\........\TOPsheet.jhd
.............\........\TOPsheet.lso
.............\........\TOPsheet.ncd
.............\........\TOPsheet.ngc
.............\........\TOPsheet.ngd
.............\........\TOPsheet.ngr
.............\........\TOPsheet.pad
.............\........\TOPsheet.par
.............\........\TOPsheet.pcf
.............\........\TOPsheet.prj
.............\........\TOPsheet.ptwx
.............\........\TOPsheet.sch
.............\........\TOPsheet.stx
.............\........\TOPsheet.syr
.............\........\TOPsheet.twr
.............\........\TOPsheet.twx
.............\........\TOPsheet.ucf
.............\........\TOPsheet.unroutes
.............\........\TOPsheet.ut
.............\........\TOPsheet.vhf
.............\........\TOPsheet.xpi
.............\........\TOPsheet.xst
.............\........\TOPsheet_bitgen.xwbt
.............\........\TOPsheet_envsettings.html
.............\........\TOPsheet_guide.ncd
.............\........\TOPsheet_map.map
.............\........\TOPsheet_map.mrp
.............\........\TOPsheet_map.ncd
.............\........\TOPsheet_map.ngm
.............\........\TOPsheet_map.xrpt
.............\........\TOPsheet_ngdbuild.xrpt
.............\........\TOPsheet_pad.csv
.............\........\TOPsheet_pad.txt
.............\........\TOPsheet_par.xrpt
.............\........\TOPsheet_summary.html
.............\........\TOPsheet_summary.xml
.............\........\TOPsheet_usage.xml
.............\........\TOPsheet_vhdl.prj
.............\........\TOPsheet_xst.xrpt
.............\........\webtalk.log
.............\........\webtalk_pn.xml
.............\........\xlnx_auto_0_xdb\cst.xbcd
.............\........\.st\work\hdllib.ref
.............\........\...\....\hdpdeps.ref
.............\........\...\....\sub00\vhpl00.vho
.............\........\...\....\.....\vhpl01.vho
.............\........\...\....\.....\vhpl02.vho
.............\........\...\....\.....\vhpl03.vho
.
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