- Category:
- VHDL-FPGA-Verilog
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- File Size:
- 4kb
- Update:
- 2015-04-21
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- Uploaded by:
- 张浩阳
Description: CAN bus, DSP+ FPGA+ SJA1000 architecture, FPGA logic is responsible for the design, FPGA is responsible in this document have dsp and sja1000 Communications
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