Description: Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code. I believe you will like it.
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File list (Check if you may need any files):
async_fifo_prj
..............\doc
..............\...\异步FIFO设计.doc
..............\imp
..............\...\Top_MyFIFO_Ctrl.asm.rpt
..............\...\Top_MyFIFO_Ctrl.done
..............\...\Top_MyFIFO_Ctrl.eda.rpt
..............\...\Top_MyFIFO_Ctrl.fit.rpt
..............\...\Top_MyFIFO_Ctrl.fit.smsg
..............\...\Top_MyFIFO_Ctrl.fit.summary
..............\...\Top_MyFIFO_Ctrl.flow.rpt
..............\...\Top_MyFIFO_Ctrl.jdi
..............\...\Top_MyFIFO_Ctrl.map.rpt
..............\...\Top_MyFIFO_Ctrl.map.summary
..............\...\Top_MyFIFO_Ctrl.pin
..............\...\Top_MyFIFO_Ctrl.qpf
..............\...\Top_MyFIFO_Ctrl.qsf
..............\...\Top_MyFIFO_Ctrl.sof
..............\...\Top_MyFIFO_Ctrl.sta.rpt
..............\...\Top_MyFIFO_Ctrl.sta.summary
..............\...\Top_MyFIFO_Ctrl_assignment_defaults.qdf
..............\...\blk_mem_gen_v2_7.qip
..............\...\blk_mem_gen_v2_7.v
..............\...\blk_mem_gen_v2_7_bb.v
..............\...\blk_mem_gen_v2_7_inst.v
..............\...\db
..............\...\..\Top_MyFIFO_Ctrl.db_info
..............\...\..\Top_MyFIFO_Ctrl.sld_design_entry.sci
..............\...\..\altsyncram_kkj1.tdf
..............\...\..\logic_util_heursitic.dat
..............\...\..\prev_cmp_Top_MyFIFO_Ctrl.qmsg
..............\...\greybox_tmp
..............\...\...........\cbx_args.txt
..............\...\incremental_db
..............\...\..............\README
..............\...\..............\compiled_partitions
..............\...\..............\...................\Top_MyFIFO_Ctrl.db_info
..............\...\simulation
..............\...\..........\modelsim
..............\...\..........\........\Top_MyFIFO_Ctrl.sft
..............\...\..........\........\Top_MyFIFO_Ctrl.vho
..............\...\..........\........\Top_MyFIFO_Ctrl_8_1200mv_0c_slow.vho
..............\...\..........\........\Top_MyFIFO_Ctrl_8_1200mv_0c_vhd_slow.sdo
..............\...\..........\........\Top_MyFIFO_Ctrl_8_1200mv_85c_slow.vho
..............\...\..........\........\Top_MyFIFO_Ctrl_8_1200mv_85c_vhd_slow.sdo
..............\...\..........\........\Top_MyFIFO_Ctrl_min_1200mv_0c_fast.vho
..............\...\..........\........\Top_MyFIFO_Ctrl_min_1200mv_0c_vhd_fast.sdo
..............\...\..........\........\Top_MyFIFO_Ctrl_modelsim.xrf
..............\...\..........\........\Top_MyFIFO_Ctrl_vhd.sdo
..............\sim
..............\...\tb_Top_MyFIFO_Ctrl.cr.mti
..............\...\tb_Top_MyFIFO_Ctrl.mpf
..............\...\vsim.wlf
..............\...\work
..............\...\....\@gray2@norm
..............\...\....\...........\_primary.dat
..............\...\....\...........\_primary.dbs
..............\...\....\...........\_primary.vhd
..............\...\....\...........\verilog.prw
..............\...\....\...........\verilog.psm
..............\...\....\@my@f@i@f@o1024x8
..............\...\....\.................\_primary.dat
..............\...\....\.................\_primary.dbs
..............\...\....\.................\_primary.vhd
..............\...\....\.................\verilog.prw
..............\...\....\.................\verilog.psm
..............\...\....\@my@f@i@f@o_@ctrl
..............\...\....\.................\_primary.dat
..............\...\....\.................\_primary.dbs
..............\...\....\.................\_primary.vhd
..............\...\....\.................\verilog.prw
..............\...\....\.................\verilog.psm
..............\...\....\@norm2@gray
..............\...\....\...........\_primary.dat
..............\...\....\...........\_primary.dbs
..............\...\....\...........\_primary.vhd
..............\...\....\...........\verilog.prw
..............\...\....\...........\verilog.psm
..............\...\....\@prbs@any@checker
..............\...\....\.................\_primary.dat
..............\...\....\.................\_primary.dbs
..............\...\....\.................\_primary.vhd
..............\...\....\.................\verilog.prw
..............\...\....\.................\verilog.psm
..............\...\....\@prbs@any@generator
..............\...\....\...................\_primary.dat
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