Description: I am a 2014 graduate of Fudan University. This is an 8-bit CPU design VHDL implementation. The CPU based on RISC architecture to achieve the basic functions, such as cpu: arithmetic operations, jumps and so on. In addition, there are a ROM area 17, is stored in the instruction. You can write some 17 of the instruction code, and placed in the ROM area, the CPU will automatically run the result. Compression bag is the source code and design requirements of our time. When the final commissioning source code is placed in the address 0 17 of Fibonacci numbers (Fibonacci Numbers) instruction. You can see the results of the simulation by modelsim.
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File list (Check if you may need any files):
CPU\CPU Title.pdf
...\cpu
...\...\ALU.vhd
...\...\ALU_tb.vhd
...\...\IDU.vhd
...\...\IDU_tb.vhd
...\...\inst_ROM.vhd
...\...\inst_ROM_tb.vhd
...\...\MicroController.vhd
...\...\MicroController_sources.f
...\...\MicroController_tb.vhd
...\...\Register_Bank.vhd
...\...\Register_Bank_tb.vhd
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