Description: The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock
group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by
four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of
the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock
Group must be equal to or less than that of the Fast Peripherals Clock Group.
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fec_code.c
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