Description: THIS PROJECT IMPLEMENTED ON VITERX 4 FPGA and THE COMPLETE SOURCE FILES testbench, design file UCF file are there and THIS ADC is maily configured with SPI protocol interface SPI CLK,SPI DATA, SPI LE, the SPEED OF OPERATION OF SPI CLK is 10 MHZ
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File list (Check if you may need any files):
ADC_AD7490\AD7490.pdf
..........\ADC_CONTROLLER.vhd
..........\TEST_ADC_CONTROLLER_tb.vhd
..........\top_adc_module.drc
..........\TOP_ADC_MODULE.ucf
..........\TOP_ADC_MODULE.vhd
ADC_AD7490
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