Description: The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used directly to comprehensive post
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CAVLE h264
..........\CAVLC_VHDL.txt
..........\cavlc
..........\.....\branches
..........\.....\tags
..........\.....\trunk
..........\.....\.....\bench
..........\.....\.....\.....\cavlc_tb.v
..........\.....\.....\.....\input_gen
..........\.....\.....\.....\.........\linux.out
..........\.....\.....\.....\.........\test.264
..........\.....\.....\.....\.........\win32.exe
..........\.....\.....\.....\tests
..........\.....\.....\.....\.....\akiyo
..........\.....\.....\.....\.....\.....\c_out.txt
..........\.....\.....\.....\.....\.....\in.txt
..........\.....\.....\.....\.....\.....\out.txt
..........\.....\.....\.....\.....\formam
..........\.....\.....\.....\.....\......\c_out.txt
..........\.....\.....\.....\.....\......\log.txt
..........\.....\.....\.....\.....\parkrun
..........\.....\.....\.....\.....\.......\c_out.txt
..........\.....\.....\.....\.....\.......\in.txt
..........\.....\.....\rtl
..........\.....\.....\...\cavlc_fsm.v
..........\.....\.....\...\cavlc_len_gen.v
..........\.....\.....\...\cavlc_read_levels.v
..........\.....\.....\...\cavlc_read_run_befores.v
..........\.....\.....\...\cavlc_read_total_coeffs.v
..........\.....\.....\...\cavlc_read_total_zeros.v
..........\.....\.....\...\cavlc_top.v
..........\.....\.....\...\defines.v
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