FPGA控制DM9000A进行以太网数据收发的Verilog实现
..............................................\Dm9000a
..............................................\DM9000A.C
..............................................\DM9000A.H
..............................................\DM9000A.pdf
..............................................\.m9000a\Dm9000a.def
..............................................\.......\Dm9000a_Init.v
..............................................\.......\Dm9000a_IO.v
..............................................\.......\Dm9000a_Ior.v
..............................................\.......\Dm9000a_IORD.v
..............................................\.......\Dm9000a_Iow.v
..............................................\.......\Dm9000a_IOWR.v
..............................................\.......\phy_write.v
..............................................\.......\vssver.scc
..............................................\Dm9000a和FPGA的接口全图.jpg
..............................................\FPGA控制DM9000A进行以太网数据收发的Verilog实现 - 恋恋风尘.mht
..............................................\Test
..............................................\....\Dm9000a_Init
..............................................\....\............\db
..............................................\....\............\..\Dm9000a_Init.db_info
..............................................\....\............\Dm9000a_Init.asm.rpt
..............................................\....\............\Dm9000a_Init.done
..............................................\....\............\Dm9000a_Init.fit.rpt
..............................................\....\............\Dm9000a_Init.fit.smsg
..............................................\....\............\Dm9000a_Init.fit.summary
..............................................\....\............\Dm9000a_Init.flow.rpt
..............................................\....\............\Dm9000a_Init.map.rpt
..............................................\....\............\Dm9000a_Init.map.smsg
..............................................\....\............\Dm9000a_Init.map.summary
..............................................\....\............\Dm9000a_Init.pin
..............................................\....\............\Dm9000a_Init.pof
..............................................\....\............\Dm9000a_Init.qpf
..............................................\....\............\Dm9000a_Init.qsf
..............................................\....\............\Dm9000a_Init.qws
..............................................\....\............\Dm9000a_Init.sof
..............................................\....\............\Dm9000a_Init.tan.rpt
..............................................\....\............\Dm9000a_Init.tan.summary
..............................................\....\............\Dm9000a_Init.vwf
..............................................\....\............\Dm9000a_Init_Test.v
..............................................\....\............\vssver.scc
..............................................\....\Dm9000a_IO
..............................................\....\Dm9000a_Ior
..............................................\....\Dm9000a_IORD
..............................................\....\............\Dm9000a_IORD_Test.qpf
..............................................\....\............\Dm9000a_IORD_Test.qsf
..............................................\....\............\Dm9000a_IORD_Test.v
..............................................\....\............\Dm9000a_IORD_Test.vwf
..............................................\....\............\vssver.scc
..............................................\....\.........or\Dm9000a_Ior.qpf
..............................................\....\...........\Dm9000a_Ior.qsf
..............................................\....\...........\Dm9000a_Ior.qws
..............................................\....\...........\Dm9000a_Ior.vwf
..............................................\....\...........\vssver.scc
.........................................