Title:
sync-and-asyn_FIFO_verilog
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Description: Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
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rptr_empty.v
wptr_full.v
sync_w2r_tb.v
sync_w2r.v
async_fifo_beha.v
async_fifo_beha_tb.v
asynchronous_fifo1.v
asynchronous_fifo1_tb.v
wptr_full_tb.v
rptr_empty_tb.v
sync_r2w.v
sync_r2w_tb.v
001-FPGA学习小结(FIFO)-陈建军.pdf
001-Simulation_and_Synthesis_Techniques_for_Async_FIFO_Design_with_Asynchronous_Pointer_Comparisons.pdf
001-Simulation_and_Synthesis_Techniques_for_Asynchronous_FIFO_Design.pdf
同步与异步FIFO的verilog实现-2013-05-22.docx
001-FIFO经验谈-含有实例分析.pdf
