Title:
Verilog-coding-style-in-asic-design
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- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 164kb
- Update:
- 2013-05-06
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- Uploaded by:
- 江豪
Description: This document describes the verilog coding style in asic design.
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Verilog编码规范.docx
