ddr(双速率)sdram控制器参考设计及代码\doc\ddr_sdram.pdf
....................................\model\mt46v4m16.v
....................................\readme.txt
....................................\.oute\db\ddr_sdram.db_info
....................................\.....\..\ddr_sdram.eco.cdb
....................................\.....\..\ddr_sdram.sld_design_entry.sci
....................................\.....\.dr_sdram.bak\ddr_sdram.csf
....................................\.....\.............\ddr_sdram.esf
....................................\.....\.............\ddr_sdram.psf
....................................\.....\.............\ddr_sdram.quartus
....................................\.....\ddr_sdram.csf
....................................\.....\ddr_sdram.esf
....................................\.....\ddr_sdram.psf
....................................\.....\ddr_sdram.qpf
....................................\.....\ddr_sdram.qsf
....................................\.....\ddr_sdram.qws
....................................\.....\ddr_sdram.vqm
....................................\.....\pll1.v
....................................\simulation\ddr_compile_all.v
....................................\..........\ddr_sdram_tb.v
....................................\..........\modelsim.ini
....................................\..........\readme.txt
....................................\..........\work\altclklock\verilog.psm
....................................\..........\....\..........\_primary.dat
....................................\..........\....\..........\_primary.vhd
....................................\..........\....\ddr_command\verilog.psm
....................................\..........\....\...........\_primary.dat
....................................\..........\....\...........\_primary.vhd
....................................\..........\....\......ntrol_interface\verilog.psm
....................................\..........\....\.....................\_primary.dat
....................................\..........\....\.....................\_primary.vhd
....................................\..........\....\....data_path\verilog.psm
....................................\..........\....\.............\_primary.dat
....................................\..........\....\.............\_primary.vhd
....................................\..........\....\....sdram\verilog.psm
....................................\..........\....\.........\_primary.dat
....................................\..........\....\.........\_primary.vhd
....................................\..........\....\........._tb\verilog.psm
....................................\..........\....\............\_primary.dat
....................................\..........\....\............\_primary.vhd
....................................\..........\....\mt46v4m16\verilog.psm
....................................\..........\....\.........\_primary.dat
....................................\..........\....\.........\_primary.vhd
....................................\..........\....\pll1\verilog.psm
....................................\..........\....\....\_primary.dat
....................................\..........\....\....\_primary.vhd
....................................\..........\....\_info
....................................\.ource\altclklock.v
....................................\......\ddr_Command.v
....................................\......\ddr_control_interface.v
....................................\......\ddr_data_path.v
....................................\......\ddr_sdram.v
....................................\......\Params.v
....................................\......\pll1.v
....................................\.ynthesis\synplicity\ddr_data_path.srm
....................................\.........\..........\ddr_data_path.srr
....................................\.........\..........\ddr_data_path.srs
....................................\.........\..........\ddr_data_path.tlg
....................................\.........\..........\ddr_data_path.xrf
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