7segment display VHDL
.....................\lab
.....................\...\counter.vhd
.....................\...\counter_t.fdo
.....................\...\counter_t.udo
.....................\...\counter_t.vhd
.....................\...\counter_t_wave.fdo
.....................\...\ipcore_dir
.....................\...\lab.gise
.....................\...\lab.ise
.....................\...\lab.xise
.....................\...\lab_xdb
.....................\...\.......\tmp
.....................\...\.......\...\ise
.....................\...\.......\...\ise.lock
.....................\...\.......\...\...\version
.....................\...\.......\...\...\__OBJSTORE__
.....................\...\.......\...\...\............\Autonym
.....................\...\.......\...\...\............\common
.....................\...\.......\...\...\............\HierarchicalDesign
.....................\...\.......\...\...\............\..................\HDProject
.....................\...\.......\...\...\............\..................\.........\HDProject
.....................\...\.......\...\...\............\..................\.........\HDProject_StrTbl
.....................\...\.......\...\...\............\..................\__stored_object_table__
.....................\...\.......\...\...\............\PnAutoRun
.....................\...\.......\...\...\............\.........\Scripts
.....................\...\.......\...\...\............\.........\.......\RunOnce_tcl
.....................\...\.......\...\...\............\.........\.......\RunOnce_tcl_StrTbl
.....................\...\.......\...\...\............\ProjectNavigator
.....................\...\.......\...\...\............\ProjectNavigator11
.....................\...\.......\...\...\............\ProjectNavigatorGui
.....................\...\.......\...\...\............\...................\CViewSelector
.....................\...\.......\...\...\............\...................\CViewSelector_StrTbl
.....................\...\.......\...\...\............\...................\File-SynthesisOnly
.....................\...\.......\...\...\............\...................\File-SynthesisOnly_StrTbl
.....................\...\.......\...\...\............\...................\Library-SynthesisOnly
.....................\...\.......\...\...\............\...................\Library-SynthesisOnly_StrTbl
.....................\...\.......\...\...\............\...................\Process-BehavioralSim-
.....................\...\.......\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE
.....................\...\.......\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl
.....................\...\.......\...\...\............\...................\Process-BehavioralSim-_StrTbl
.....................\...\.......\...\...\............\...................\Process-SynthesisOnly-
.....................\...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
.....................\...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
.....................\...\.......\...\...\............\...................\Process-SynthesisOnly-_StrTbl
.....................\...\.......\...\...\............\...................\Source-BehavioralSim-AutoCompile
.....................\...\.......\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl
.....................\...\.......\...\...\............\...................\Source-SynthesisOnly-AutoCompile
.....................\...\.......\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
.....................\...\.......\...\...\............\................\dpm_project_main
.....................\...\.......\...\...\............\................\................\dpm_project_main
.....................\...\.......\...\...\............\................\................\dpm_project_main_StrTbl
.....................\...\.......\...\...\............\xreport
....................