- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 237kb
- Update:
- 2013-09-24
- Downloads:
- 0 Times
- Uploaded by:
- 杨凯
Description: DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions
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DDR3 SDRAM Controller\DDR3 DRAM controller.docx
.....................\Test HW.jpg
.....................\TestBench
.....................\TestBench.png
.....................\Title
.....................\~$R3 DRAM controller.docx
DDR3 SDRAM Controller
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