- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2013-03-04
- Downloads:
- 0 Times
- Uploaded by:
- 电工
Description: Write VHDL 16x8 stack module design, memory signal is given full and refused to continue the deposit readout LIFO principle store data read out from the memory disappear There are corresponding testbech file, tested available. Useful for small design! Welcome Download exchanges to learn.
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stack_16x8.vhd
tb_stack_16x8.vhd
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