Final
.....\Given
.....\.....\Miniproject VGA and ROM
.....\.....\Miniproject_VGA
.....\.....\...............\MiniProject3_readme.pdf
.....\.....\...............\Mini_project_vga
.....\.....\...............\................\VGA_top_level.asm.rpt
.....\.....\...............\................\VGA_top_level.done
.....\.....\...............\................\VGA_top_level.dpf
.....\.....\...............\................\VGA_top_level.fit.rpt
.....\.....\...............\................\VGA_top_level.fit.summary
.....\.....\...............\................\VGA_top_level.flow.rpt
.....\.....\...............\................\VGA_top_level.map.rpt
.....\.....\...............\................\VGA_top_level.map.summary
.....\.....\...............\................\VGA_top_level.pin
.....\.....\...............\................\VGA_top_level.pof
.....\.....\...............\................\VGA_top_level.qpf
.....\.....\...............\................\VGA_top_level.qsf
.....\.....\...............\................\VGA_top_level.qws
.....\.....\...............\................\VGA_top_level.sof
.....\.....\...............\................\VGA_top_level.tan.rpt
.....\.....\...............\................\VGA_top_level.tan.summary
.....\.....\...............\................\VGA_top_level.vhd
.....\.....\...............\................\colorROM.cmp
.....\.....\...............\................\colorROM.mif
.....\.....\...............\................\colorROM.qip
.....\.....\...............\................\colorROM.vhd
.....\.....\...............\................\db
.....\.....\...............\................\..\VGA_top_level.cbx.xml
.....\.....\...............\................\..\VGA_top_level.cmp.rdb
.....\.....\...............\................\..\VGA_top_level.db_info
.....\.....\...............\................\..\VGA_top_level.eco.cdb
.....\.....\...............\................\..\VGA_top_level.hier_info
.....\.....\...............\................\..\VGA_top_level.hif
.....\.....\...............\................\..\VGA_top_level.lpc.html
.....\.....\...............\................\..\VGA_top_level.lpc.rdb
.....\.....\...............\................\..\VGA_top_level.lpc.txt
.....\.....\...............\................\..\VGA_top_level.map.ecobp
.....\.....\...............\................\..\VGA_top_level.map.kpt
.....\.....\...............\................\..\VGA_top_level.map.qmsg
.....\.....\...............\................\..\VGA_top_level.map_bb.cdb
.....\.....\...............\................\..\VGA_top_level.map_bb.hdb
.....\.....\...............\................\..\VGA_top_level.map_bb.logdb
.....\.....\...............\................\..\VGA_top_level.pre_map.cdb
.....\.....\...............\................\..\VGA_top_level.pre_map.hdb
.....\.....\...............\................\..\VGA_top_level.rtlv.hdb
.....\.....\...............\................\..\VGA_top_level.rtlv_sg.cdb
.....\.....\...............\................\..\VGA_top_level.rtlv_sg_swap.cdb
.....\.....\...............\................\..\VGA_top_level.sgdiff.cdb
.....\.....\...............\................\..\VGA_top_level.sgdiff.hdb
.....\.....\...............\................\..\VGA_top_level.sld_design_entry.sci
.....\.....\...............\................\..\VGA_top_level.sld_design_entry_dsc.sci
.....\.....\...............\................\..\VGA_top_level.syn_hier_info
.....\.....\...............\................\..\VGA_top_level.tis_db_list.ddb
.....\.....\...............\................\..\altsyncram_pv71.tdf
.....\.....\...............\................\..\logic_util_heursitic.dat
.....\.....\...............\................\..\prev_cmp_VGA_top_level.asm.qmsg
.....\.....\...............\................\..\prev_cmp_VGA_top_level.fit.qmsg
.....\.....\...............\................\..\prev_cmp_VGA_top_level.map.qmsg
.....\.....\...............\................\..\prev_cmp_VGA_top_level.qmsg
.....\.....\...............\................\..\prev_cmp_VGA_top_level.tan.qmsg
.....\.....\...............\................\incremental_db
.....\.....\..