- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 338kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- 陈小龙
Description: Vhdl design digital display stopwatch accurate timing and display boot display 00.00.00 Users can be cleared at any time, suspend, timing 59 minutes maximum chronograph, accurate to 0.01 seconds minimum.
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File list (Check if you may need any files):
watch\U0384339.DLS
.....\bai.acf
.....\bai.vhd
.....\miao.hif
.....\miao.ndb
.....\miao.fit
.....\miao.pin
.....\miao.sof
.....\miao.snf
.....\miao.rpt
.....\miao.pof
.....\miao.hex
.....\miao.ttf
.....\miao.scf
.....\BAI.sym
.....\U1613030.DLS
.....\U3007596.DLS
.....\bai.hif
.....\miao.mmf
.....\hou.acf
.....\U6817358.DLS
.....\hou.vhd
.....\hou.mmf
.....\U9889589.DLS
.....\U2463266.DLS
.....\bai.pin
.....\U2804089.DLS
.....\bai.fit
.....\bai.ndb
.....\bai.snf
.....\HOU.sym
.....\bai.sof
.....\bai.pof
.....\bai.hex
.....\bai.ttf
.....\bai.scf
.....\hou.hif
.....\hou.ndb
.....\hou.fit
.....\hou.pin
.....\hou.sof
.....\hou.snf
.....\hou.rpt
.....\hou.pof
.....\hou.hex
.....\hou.ttf
.....\hou.scf
.....\dou.acf
.....\dou.vhd
.....\dou.mmf
.....\U6102961.DLS
.....\U8383696.DLS
.....\U7886060.DLS
.....\DOU.sym
.....\dou.hif
.....\dou.ndb
.....\dou.fit
.....\dou.pin
.....\dou.sof
.....\dou.snf
.....\dou.rpt
.....\dou.pof
.....\dou.hex
.....\bai.mmf
.....\dou.ttf
.....\dou.scf
.....\aab.acf
.....\aab.vhd
.....\LIB.DLS
.....\aab.mmf
.....\bbc.rpt
.....\aab.hif
.....\U7725208.DLS
.....\U4003622.DLS
.....\U2859821.DLS
.....\U8081214.DLS
.....\AAB.sym
.....\aab.ndb
.....\aab.fit
.....\aab.pin
.....\aab.sof
.....\aab.snf
.....\aab.rpt
.....\aab.pof
.....\aab.hex
.....\aab.ttf
.....\aab.scf
.....\sel.acf
.....\bai.rpt
.....\sel.vhd
.....\miao.acf
.....\miao.vhd
.....\disp.acf
.....\disp.vhd
.....\disp.mmf
.....\U0568612.DLS
.....\SEL.sym
.....\sel.hif
.....\disp.hif
.....\U5688779.DLS
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