Description:
File/Directory Description
=============================================================================
\doc DDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the verilog testbench, modelsim project file, and library
\source Contains the verilog source files for the DDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
To Search:
File list (Check if you may need any files):
dab1814114c3
............\doc
............\...\ddr_sdram.pdf
............\model
............\.....\mt46v4m16.v
............\readme.txt
............\route
............\.....\ddr_sdram.csf
............\.....\ddr_sdram.esf
............\.....\ddr_sdram.psf
............\.....\ddr_sdram.quartus
............\.....\ddr_sdram.vqm
............\.....\pll1.v
............\simulation
............\..........\ddr_compile_all.v
............\..........\ddr_sdram_tb.v
............\..........\modelsim.ini
............\..........\readme.txt
............\..........\work
............\..........\....\altclklock
............\..........\....\..........\verilog.psm
............\..........\....\..........\_primary.dat
............\..........\....\..........\_primary.vhd
............\..........\....\ddr_command
............\..........\....\...........\verilog.psm
............\..........\....\...........\_primary.dat
............\..........\....\...........\_primary.vhd
............\..........\....\ddr_control_interface
............\..........\....\.....................\verilog.psm
............\..........\....\.....................\_primary.dat
............\..........\....\.....................\_primary.vhd
............\..........\....\ddr_data_path
............\..........\....\.............\verilog.psm
............\..........\....\.............\_primary.dat
............\..........\....\.............\_primary.vhd
............\..........\....\ddr_sdram
............\..........\....\.........\verilog.psm
............\..........\....\.........\_primary.dat
............\..........\....\.........\_primary.vhd
............\..........\....\ddr_sdram_tb
............\..........\....\............\verilog.psm
............\..........\....\............\_primary.dat
............\..........\....\............\_primary.vhd
............\..........\....\mt46v4m16
............\..........\....\.........\verilog.psm
............\..........\....\.........\_primary.dat
............\..........\....\.........\_primary.vhd
............\..........\....\pll1
............\..........\....\....\verilog.psm
............\..........\....\....\_primary.dat
............\..........\....\....\_primary.vhd
............\..........\....\_info
............\source
............\......\altclklock.v
............\......\ddr_Command.v
............\......\ddr_control_interface.v
............\......\ddr_data_path.v
............\......\ddr_sdram.v
............\......\Params.v
............\......\pll1.v
............\synthesis
............\.........\synplicity
............\.........\..........\ddr_data_path.srm
............\.........\..........\ddr_data_path.srr
............\.........\..........\ddr_data_path.srs
............\.........\..........\ddr_data_path.tlg
............\.........\..........\ddr_data_path.xrf
............\.........\..........\ddr_sdram.prj
............\.........\..........\ddr_sdram.sdc
............\.........\..........\ddr_sdram.srm
............\.........\..........\ddr_sdram.srr
............\.........\..........\ddr_sdram.srs
............\.........\..........\ddr_sdram.tcl
............\.........\..........\ddr_sdram.tlg
............\.........\..........\ddr_sdram.vqm
............\.........\..........\ddr_sdram.xrf
............\.........\..........\ddr_sdram_cons.tcl
............\.........\..........\ddr_sdram_rm.tcl
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