- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 13kb
- Update:
- 2013-01-05
- Downloads:
- 1 Times
- Uploaded by:
- 王力
Description: Using VHDL language 33 square root carry select adder, to meet in the 500M clock work correctly, use the DB test, and through imitation.
To Search:
File list (Check if you may need any files):
33 square root\test.vhd
..............\adder.vhd
..............\fulladd.vhd
..............\nadd.vhd
..............\netlist.sdf
..............\netlist.vhd
33 square root
Download