- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 44kb
- Update:
- 2012-12-16
- Downloads:
- 0 Times
- Uploaded by:
- 工程师
Description: This program is implemented with VHDL stopwatch, low-speed clock master clock divider to debug through, we can refer to.
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Second_VHDL\db\miaobiao.db_info
...........\..\miaobiao.eco.cdb
...........\..\miaobiao.sld_design_entry.sci
...........\db
...........\miaobiao.asm.rpt
...........\miaobiao.cdf
...........\miaobiao.done
...........\miaobiao.dpf
...........\miaobiao.fit.rpt
...........\miaobiao.fit.smsg
...........\miaobiao.fit.summary
...........\miaobiao.flow.rpt
...........\miaobiao.map.rpt
...........\miaobiao.map.summary
...........\miaobiao.pin
...........\miaobiao.pof
...........\miaobiao.qpf
...........\miaobiao.qsf
...........\miaobiao.qws
...........\miaobiao.sof
...........\miaobiao.tan.rpt
...........\miaobiao.tan.summary
...........\miaobiao.vhd
...........\miaobiao_assignment_defaults.qdf
Second_VHDL
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