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Title: uart Download
  • Category:
  • VHDL-FPGA-Verilog
  • Tags:
  • File Size:
  • 23kb
  • Update:
  • 2012-12-02
  • Downloads:
  • 0 Times
  • Uploaded by:
  • sun
 Description: Design based on the Universal Serial Bus XILINX+ISE
 Downloaders recently: [More information of uploader sun]
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通用串行总线\automake.log
............\baudrate_generator.jhd
............\baudrate_generator.vhd
............\baudrate_generator_TB.jhd
............\baudrate_generator_TB.vhd
............\counter.jhd
............\counter.vhd
............\counter_TB.jhd
............\counter_TB.vhd
............\detector.jhd
............\detector.vhd
............\detector_TB.jhd
............\detector_TB.vhd
............\parity_verifier.jhd
............\parity_verifier.vhd
............\parity_verifier_TB.jhd
............\parity_verifier_TB.vhd
............\shift_register.jhd
............\shift_register.vhd
............\shift_register_TB.jhd
............\shift_register_TB.vhd
............\switch.jhd
............\switch.vhd
............\switch_bus.jhd
............\switch_bus.vhd
............\switch_bus_TB.jhd
............\switch_bus_TB.vhd
............\UART.npl
............\uart_core.jhd
............\uart_core.vhd
............\UART_PACKAGE.vhd
............\uart_top.jhd
............\uart_top.vhd
............\uart_top_tb.jhd
............\uart_top_tb.vhd
............\__projnav\p00p5000.kis
............\.........\p00pi000.kis
............\.........\p00pl000.kis
............\.........\runXst_tcl.rsp
............\__projnav.log
............\__projnav
通用串行总线
    

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