UART\UART\designer\impl1\designer.log
....\....\........\.....\uart_test.adb
....\....\........\.....\..........dtf\verify.log
....\....\........\.....\uart_test.ide_des
....\....\........\.....\uart_test.stp
....\....\........\.....\uart_test.tcl
....\....\hdl\rec.v
....\....\...\send.v
....\....\...\uart_test.v
....\....\simulation\meminit.dat
....\....\..........\modelsim.ini
....\....\..........\modelsim.ini.sav
....\....\.martgen\smartgen.aws
....\....\.ynthesis\.recordref
....\....\.........\stdout.log
....\....\.........\.yntmp\sap.log
....\....\.........\......\uart_test.msg
....\....\.........\......\uart_test.plg
....\....\.........\traplog.tlg
....\....\.........\uart_test.areasrr
....\....\.........\uart_test.edn
....\....\.........\uart_test.fse
....\....\.........\uart_test.map
....\....\.........\uart_test.sdf
....\....\.........\uart_test.srd
....\....\.........\uart_test.srm
....\....\.........\uart_test.srr
....\....\.........\uart_test.srs
....\....\.........\uart_test.tlg
....\....\.........\uart_test_sdc.sdc
....\....\.........\uart_test_syn.prd
....\....\.........\uart_test_syn.prj
....\....\UART.prj
....\....\UART.prj.convert.7.3.bak
....\....\viewdraw\vf\project.lst
....\....\........\viewdraw.ini
....\UART实验例程.pdf
....\....\designer\impl1\simulation
....\....\........\.....\uart_test.dtf
....\....\........\impl1
....\....\synthesis\syntmp
....\....\viewdraw\sch
....\....\........\sym
....\....\........\vf
....\....\........\wir
....\....\component
....\....\constraint
....\....\coreconsole
....\....\designer
....\....\hdl
....\....\phy_synthesis
....\....\simulation
....\....\smartgen
....\....\stimulus
....\....\synthesis
....\....\viewdraw
....\UART
UART